Matt Papageorge has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42567 )
Change subject: soc/amd/picasso: Populate EFS SPI values ......................................................................
soc/amd/picasso: Populate EFS SPI values
The Embedded Firmware Structure should contain various SPI parameters for the PSP to program. This information is currently only programmed at run-time. This change is to also populate them at build time as well.
BUG=b:158755102 TEST=Read EFS values at appropriate offsets using a hex editor. Boot test on Tremblye and Morphius.
Signed-off-by: Matt Papageorge matt.papageorge@amd.corp-partner.google.com Change-Id: I78558fa3fa27c70820f0f3d636544127adab6f8b --- M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/Makefile.inc 2 files changed, 49 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/42567/1
diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index dd5731d..963b329a 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -362,6 +362,39 @@ removes arbitration with board and assumes the chipset controls the SPI flash bus entirely.
+config EFS_SPI_READ_MODE + hex + default 0x2 + help + SPI Read Mode: + 000b Normal Read (up to 33M) + 001b Reserved + 010b Dual IO (1-1-2) + 011b Quad IO (1-1-4) + 100b Dual IO (1-2-2) + 101b Quad IO (1-4-4) + 110b Normal Read (up to 66M) + 111b Fast Read + +config EFS_SPI_SPEED + hex + default 0x0 + help + FastSpeedNew value: + 0000b 66.66Mhz + 0001b 33.33MHz + 0010b 22.22MHz + 0011b 16.66MHz + 0100b 100MHz + 0101b 800KHz + +config EFS_SPI_QUAD_DUMMY_CYCLE + hex + default 0xa + help + Dummy cycle configure. For SPI chips from Micron this value should + be 0x0A. Otherwise it should be 0xFF. + config MAINBOARD_POWER_RESTORE def_bool n help diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 796f77c..9dee50b 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -237,6 +237,13 @@ $(foreach bit,$(PSP_SOFTFUSE_BITS),$(call set-bit,$(bit)))); printf "0x%x" $$A)
# +# SOC family and model info +# +SOC_FAMILY=0x17 +SOC_MODEL_MIN=0x0 +SOC_MODEL_MAX=0x2f + +# # Build the arguments to amdfwtool (order is unimportant). Missing file names # result in empty OPT_ variables, i.e. the argument is not passed to amdfwtool. # @@ -269,6 +276,9 @@ OPT_ABL5_FILE=$(call add_opt_prefix, $(PSP_ABL5_FILE), --abl-image) OPT_ABL6_FILE=$(call add_opt_prefix, $(PSP_ABL6_FILE), --abl-image) OPT_ABL7_FILE=$(call add_opt_prefix, $(PSP_ABL7_FILE), --abl-image) +OPT_EFS_SPI_READ_MODE=$(call add_opt_prefix, $(CONFIG_EFS_SPI_READ_MODE), --spi-read-mode) +OPT_EFS_SPI_SPEED=$(call add_opt_prefix, $(CONFIG_EFS_SPI_SPEED), --spi-speed) +OPT_EFS_SPI_QUAD_DUMMY_CYCLE=$(call add_opt_prefix, $(CONFIG_EFS_SPI_QUAD_DUMMY_CYCLE), --spi-micron-flag) OPT_WHITELIST_FILE=$(call add_opt_prefix, $(PSP_WHITELIST_FILE), --whitelist)
OPT_PSP_APCB_FILES=$(foreach i, $(shell seq $(words $(PSP_APCB_FILES))), \ @@ -420,6 +430,12 @@ --combo-capable \ $(OPT_TOKEN_UNLOCK) \ --flashsize $(CONFIG_ROM_SIZE) \ + $(OPT_EFS_SPI_READ_MODE) \ + $(OPT_EFS_SPI_SPEED) \ + $(OPT_EFS_SPI_QUAD_DUMMY_CYCLE) \ + --soc-family $(SOC_FAMILY) \ + --soc-model-min $(SOC_MODEL_MIN) \ + --soc-model-max $(SOC_MODEL_MAX) \ --location $(shell printf "0x%x" $(PICASSO_FWM_POSITION)) \ --output $@
Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Marshall Dawson, Aaron Durbin, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42567
to look at the new patch set (#2).
Change subject: soc/amd/picasso: Populate EFS SPI values ......................................................................
soc/amd/picasso: Populate EFS SPI values
The Embedded Firmware Structure should contain various SPI parameters for the PSP to program. This information is currently only programmed at run-time. This change is to also populate them at build time as well.
BUG=b:158755102 TEST=Read EFS values at appropriate offsets using a hex editor. Boot test on Tremblye and Morphius.
Signed-off-by: Matt Papageorge matt.papageorge@amd.corp-partner.google.com Change-Id: I78558fa3fa27c70820f0f3d636544127adab6f8b --- M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/Makefile.inc 2 files changed, 51 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/42567/2
Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42567 )
Change subject: soc/amd/picasso: Populate EFS SPI values ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42567/2/src/soc/amd/picasso/Kconfig File src/soc/amd/picasso/Kconfig:
https://review.coreboot.org/c/coreboot/+/42567/2/src/soc/amd/picasso/Kconfig... PS2, Line 367: config Could you make this a choice?
Matt Papageorge has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42567 )
Change subject: soc/amd/picasso: Populate EFS SPI values ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42567/2/src/soc/amd/picasso/Kconfig File src/soc/amd/picasso/Kconfig:
https://review.coreboot.org/c/coreboot/+/42567/2/src/soc/amd/picasso/Kconfig... PS2, Line 367: config
Could you make this a choice?
I can definitely give it a try.
Originally I did not see many good 'choice' examples to learn from aside from the kconfig documentation itself. But now I see that there have been a few checked in since I originally uploaded this patch
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42567 )
Change subject: soc/amd/picasso: Populate EFS SPI values ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42567/2/src/soc/amd/picasso/Kconfig File src/soc/amd/picasso/Kconfig:
https://review.coreboot.org/c/coreboot/+/42567/2/src/soc/amd/picasso/Kconfig... PS2, Line 373: value common_config.spi_config Shouldn’t this be configurable in one place only?
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42567 )
Change subject: soc/amd/picasso: Populate EFS SPI values ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42567/2/src/soc/amd/picasso/Kconfig File src/soc/amd/picasso/Kconfig:
https://review.coreboot.org/c/coreboot/+/42567/2/src/soc/amd/picasso/Kconfig... PS2, Line 373: value common_config.spi_config
Shouldn’t this be configurable in one place only?
Not for this change, but can we drop the entries in devicetree completely and simply use the values in EFS both for PSP and for coreboot?
Matt Papageorge has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42567 )
Change subject: soc/amd/picasso: Populate EFS SPI values ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42567/2/src/soc/amd/picasso/Kconfig File src/soc/amd/picasso/Kconfig:
https://review.coreboot.org/c/coreboot/+/42567/2/src/soc/amd/picasso/Kconfig... PS2, Line 373: value common_config.spi_config
Not for this change, but can we drop the entries in devicetree completely and simply use the values […]
next revision I will add another patch at the end of this chain to accomplish this
Hello build bot (Jenkins), Raul Rangel, Furquan Shaikh, Patrick Georgi, Martin Roth, Marshall Dawson, Nikolai Vyssotski, Aaron Durbin, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42567
to look at the new patch set (#3).
Change subject: soc/amd/picasso: Populate EFS SPI values from Kconfig options ......................................................................
soc/amd/picasso: Populate EFS SPI values from Kconfig options
The Embedded Firmware Structure should contain various SPI parameters for the PSP to program. This information is currently only programmed at run-time. This change is to populate them at build time as well.
BUG=b:158755102 TEST=Read EFS values at appropriate offsets using a hex editor. Boot test on Tremblye and Morphius.
Signed-off-by: Matt Papageorge matt.papageorge@amd.corp-partner.google.com Change-Id: I78558fa3fa27c70820f0f3d636544127adab6f8b --- M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/Makefile.inc 2 files changed, 117 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/42567/3
Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42567 )
Change subject: soc/amd/picasso: Populate EFS SPI values from Kconfig options ......................................................................
Patch Set 3:
I think we need to carry the selections that a board would use in saved config. Martin knows better than me, but I think we are limited by auto selecting options within a choice variable.
Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42567 )
Change subject: soc/amd/picasso: Populate EFS SPI values from Kconfig options ......................................................................
Patch Set 3: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/42567/3/src/soc/amd/picasso/Makefil... File src/soc/amd/picasso/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/42567/3/src/soc/amd/picasso/Makefil... PS3, Line 281: endif : ifeq else ifeq (
Hello build bot (Jenkins), Raul Rangel, Furquan Shaikh, Patrick Georgi, Martin Roth, Marshall Dawson, Nikolai Vyssotski, Aaron Durbin, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42567
to look at the new patch set (#4).
Change subject: soc/amd/picasso: Populate EFS SPI values from Kconfig options ......................................................................
soc/amd/picasso: Populate EFS SPI values from Kconfig options
The Embedded Firmware Structure should contain various SPI parameters for the PSP to program. This information is currently only programmed at run-time. This change is to populate them at build time as well.
BUG=b:158755102 TEST=Read EFS values at appropriate offsets using a hex editor. Boot test on Tremblye and Morphius.
Signed-off-by: Matt Papageorge matt.papageorge@amd.corp-partner.google.com Change-Id: I78558fa3fa27c70820f0f3d636544127adab6f8b --- M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/Makefile.inc 2 files changed, 115 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/42567/4
Hello build bot (Jenkins), Raul Rangel, Furquan Shaikh, Patrick Georgi, Martin Roth, Marshall Dawson, Nikolai Vyssotski, Aaron Durbin, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42567
to look at the new patch set (#5).
Change subject: soc/amd/picasso: Populate EFS SPI values from Kconfig options ......................................................................
soc/amd/picasso: Populate EFS SPI values from Kconfig options
The Embedded Firmware Structure should contain various SPI parameters for the PSP to program. This information is currently only programmed at run-time. This change is to populate them at build time as well.
BUG=b:158755102 TEST=Read EFS values at appropriate offsets using a hex editor. Boot test on Tremblye and Morphius.
Signed-off-by: Matt Papageorge matt.papageorge@amd.corp-partner.google.com Change-Id: I78558fa3fa27c70820f0f3d636544127adab6f8b --- M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/Makefile.inc 2 files changed, 111 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/42567/5
Hello build bot (Jenkins), Raul Rangel, Furquan Shaikh, Patrick Georgi, Martin Roth, Marshall Dawson, Nikolai Vyssotski, Aaron Durbin, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42567
to look at the new patch set (#6).
Change subject: soc/amd/picasso: Populate EFS SPI values from Kconfig options ......................................................................
soc/amd/picasso: Populate EFS SPI values from Kconfig options
The Embedded Firmware Structure should contain various SPI parameters for the PSP to program. This information is currently only programmed at run-time. This change is to populate them at build time as well.
BUG=b:158755102 TEST=Read EFS values at appropriate offsets using a hex editor. Boot test on Tremblye and Morphius.
Signed-off-by: Matt Papageorge matt.papageorge@amd.corp-partner.google.com Change-Id: I78558fa3fa27c70820f0f3d636544127adab6f8b --- M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/Makefile.inc 2 files changed, 105 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/42567/6
Matt Papageorge has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42567 )
Change subject: soc/amd/picasso: Populate EFS SPI values from Kconfig options ......................................................................
Patch Set 6:
(1 comment)
Sorry for the large number of patches, had some issues with the rebase
https://review.coreboot.org/c/coreboot/+/42567/3/src/soc/amd/picasso/Makefil... File src/soc/amd/picasso/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/42567/3/src/soc/amd/picasso/Makefil... PS3, Line 281: endif : ifeq
else ifeq (
Ack
Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42567 )
Change subject: soc/amd/picasso: Populate EFS SPI values from Kconfig options ......................................................................
Patch Set 5:
(4 comments)
https://review.coreboot.org/c/coreboot/+/42567/5/src/soc/amd/picasso/Kconfig File src/soc/amd/picasso/Kconfig:
https://review.coreboot.org/c/coreboot/+/42567/5/src/soc/amd/picasso/Kconfig... PS5, Line 369: SPI_READ_MODE_DUAL_IO_112 Is this a safe default for mandolin/cereme as well? Should we use SPI_READ_MODE_NORMAL_66M to be safe?
https://review.coreboot.org/c/coreboot/+/42567/5/src/soc/amd/picasso/Kconfig... PS5, Line 396: default Can you also add a `default SPI_SPEED_16M if EM100`
https://review.coreboot.org/c/coreboot/+/42567/5/src/soc/amd/picasso/Kconfig... PS5, Line 398: SPI_SPEED_66M If you wanted to be fancy you could add depends on !SPI_READ_MODE_NORMAL_33M
https://review.coreboot.org/c/coreboot/+/42567/5/src/soc/amd/picasso/Kconfig... PS5, Line 410: SPI_SPEED_100M depends on !SPI_READ_MODE_NORMAL_66M && !SPI_READ_MODE_NORMAL_33M
Hello build bot (Jenkins), Raul Rangel, Furquan Shaikh, Patrick Georgi, Martin Roth, Marshall Dawson, Nikolai Vyssotski, Aaron Durbin, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42567
to look at the new patch set (#7).
Change subject: soc/amd/picasso: Populate EFS SPI values from Kconfig options ......................................................................
soc/amd/picasso: Populate EFS SPI values from Kconfig options
The Embedded Firmware Structure should contain various SPI parameters for the PSP to program. This information is currently only programmed at run-time. This change is to populate them at build time as well.
BUG=b:158755102 TEST=Read EFS values at appropriate offsets using a hex editor. Boot test on Tremblye and Morphius.
Signed-off-by: Matt Papageorge matt.papageorge@amd.corp-partner.google.com Change-Id: I78558fa3fa27c70820f0f3d636544127adab6f8b --- M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/Makefile.inc 2 files changed, 109 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/42567/7
Matt Papageorge has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42567 )
Change subject: soc/amd/picasso: Populate EFS SPI values from Kconfig options ......................................................................
Patch Set 7:
(4 comments)
Updated to address feedback
https://review.coreboot.org/c/coreboot/+/42567/5/src/soc/amd/picasso/Kconfig File src/soc/amd/picasso/Kconfig:
https://review.coreboot.org/c/coreboot/+/42567/5/src/soc/amd/picasso/Kconfig... PS5, Line 369: SPI_READ_MODE_DUAL_IO_112
Is this a safe default for mandolin/cereme as well? Should we use SPI_READ_MODE_NORMAL_66M to be saf […]
Good consideration! Make sure I did it correctly, looks right based on your other feedback but it wont scale well. Choice statements dont seem to work with select unfortunately
https://review.coreboot.org/c/coreboot/+/42567/5/src/soc/amd/picasso/Kconfig... PS5, Line 396: default
Can you also add a `default SPI_SPEED_16M if EM100`
Done
https://review.coreboot.org/c/coreboot/+/42567/5/src/soc/amd/picasso/Kconfig... PS5, Line 398: SPI_SPEED_66M
If you wanted to be fancy you could add […]
Done
https://review.coreboot.org/c/coreboot/+/42567/5/src/soc/amd/picasso/Kconfig... PS5, Line 410: SPI_SPEED_100M
depends on !SPI_READ_MODE_NORMAL_66M && !SPI_READ_MODE_NORMAL_33M
Done
Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42567 )
Change subject: soc/amd/picasso: Populate EFS SPI values from Kconfig options ......................................................................
Patch Set 7: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/42567/7/src/soc/amd/picasso/Kconfig File src/soc/amd/picasso/Kconfig:
https://review.coreboot.org/c/coreboot/+/42567/7/src/soc/amd/picasso/Kconfig... PS7, Line 373: default SPI_READ_MODE_NORMAL_66M if BOARD_AMD_MANDOLIN I would add
select SPI_READ_MODE_NORMAL_66M
to the mandolin/Kconfig
I would also modify the zork/Kconfig and add SPI_READ_MODE_DUAL_IO_112 to the BOARD_SPECIFIC_OPTIONS.
Matt Papageorge has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42567 )
Change subject: soc/amd/picasso: Populate EFS SPI values from Kconfig options ......................................................................
Patch Set 8:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42567/7/src/soc/amd/picasso/Kconfig File src/soc/amd/picasso/Kconfig:
https://review.coreboot.org/c/coreboot/+/42567/7/src/soc/amd/picasso/Kconfig... PS7, Line 373: default SPI_READ_MODE_NORMAL_66M if BOARD_AMD_MANDOLIN
I would add […]
Tried this, unfortunately I cannot 'select' an option from a 'choice' statement. I get a build error
Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42567 )
Change subject: soc/amd/picasso: Populate EFS SPI values from Kconfig options ......................................................................
Patch Set 8:
(9 comments)
https://review.coreboot.org/c/coreboot/+/42567/8/src/soc/amd/picasso/Kconfig File src/soc/amd/picasso/Kconfig:
https://review.coreboot.org/c/coreboot/+/42567/8/src/soc/amd/picasso/Kconfig... PS8, Line 370: choice SPI_READ_MODE As I mention below, you could just get rid of the choice menu and have one option that lets you directly select the value.
https://review.coreboot.org/c/coreboot/+/42567/8/src/soc/amd/picasso/Kconfig... PS8, Line 373: default SPI_READ_MODE_NORMAL_66M if BOARD_AMD_MANDOLIN 1) this will never have an effect since the first default is the one that gets used. 2) Can you override this in the mandoin board instead of here?
https://doc.coreboot.org/getting_started/kconfig.html?highlight=kconfig#defa...
https://review.coreboot.org/c/coreboot/+/42567/8/src/soc/amd/picasso/Kconfig... PS8, Line 379: (1-1-2) Maybe address what each of these numbers mean in the help somewhere?
“1-1-2" means command, address and data are transmitted through 1 wire, 1 wire and 2 wire, respectively.
https://review.coreboot.org/c/coreboot/+/42567/8/src/soc/amd/picasso/Kconfig... PS8, Line 391: "Normal Read (up to 66M)" Does this mean 1-1-1?
https://review.coreboot.org/c/coreboot/+/42567/8/src/soc/amd/picasso/Kconfig... PS8, Line 397: Add EFS_SPI_READ_MODE here so it's not done in the makefile?
# Do not override this value in the mainboard - override the SPI_READ_MODE value instead. config EFS_SPI_READ_MODE int default 0 if SPI_READ_MODE_NORMAL_33M default 2 if SPI_READ_MODE_DUAL_IO_112 default 3 if SPI_READ_MODE_QUAD_IO_114 ...
Optionally, you can get rid of the choice and just use this value directly, with all of the values in the help text.
https://review.coreboot.org/c/coreboot/+/42567/8/src/soc/amd/picasso/Kconfig... PS8, Line 429: Should be set if Micron parts are used for the BIOS SPI chip I'd like to understand more about this option. What are the downsides to selecting always? If there are no downsides, why have the option?
https://review.coreboot.org/c/coreboot/+/42567/8/src/soc/amd/picasso/Kconfig... PS8, Line 435: are always be used "may always be used?"
https://review.coreboot.org/c/coreboot/+/42567/8/src/soc/amd/picasso/Makefil... File src/soc/amd/picasso/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/42567/8/src/soc/amd/picasso/Makefil... PS8, Line 326: EFS_SPI_READ_MODE=0 Why not do all of these in the Kconfig instead of in the makefile?
https://review.coreboot.org/c/coreboot/+/42567/8/src/soc/amd/picasso/Makefil... PS8, Line 340: EFS_SPI_READ_MODE If you put all of that in the Kconfig file, you can just use CONFIG_EFS_SPI_READ_MODE here.
Matt Papageorge has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42567 )
Change subject: soc/amd/picasso: Populate EFS SPI values from Kconfig options ......................................................................
Patch Set 9:
(7 comments)
https://review.coreboot.org/c/coreboot/+/42567/8/src/soc/amd/picasso/Kconfig File src/soc/amd/picasso/Kconfig:
https://review.coreboot.org/c/coreboot/+/42567/8/src/soc/amd/picasso/Kconfig... PS8, Line 370: choice SPI_READ_MODE
As I mention below, you could just get rid of the choice menu and have one option that lets you dire […]
Did not know I could do that! Definitely will change it to be that way
https://review.coreboot.org/c/coreboot/+/42567/8/src/soc/amd/picasso/Kconfig... PS8, Line 373: default SPI_READ_MODE_NORMAL_66M if BOARD_AMD_MANDOLIN
- this will never have an effect since the first default is the one that gets used. […]
Fixed this thanks to your example.
https://review.coreboot.org/c/coreboot/+/42567/8/src/soc/amd/picasso/Kconfig... PS8, Line 379: (1-1-2)
Maybe address what each of these numbers mean in the help somewhere? […]
Done
https://review.coreboot.org/c/coreboot/+/42567/8/src/soc/amd/picasso/Kconfig... PS8, Line 391: "Normal Read (up to 66M)"
Does this mean 1-1-1?
I need to get answers to this
https://review.coreboot.org/c/coreboot/+/42567/8/src/soc/amd/picasso/Kconfig... PS8, Line 397:
Add EFS_SPI_READ_MODE here so it's not done in the makefile? […]
Also did not realize I could do that. This is way simpler than the makefile.
https://review.coreboot.org/c/coreboot/+/42567/8/src/soc/amd/picasso/Kconfig... PS8, Line 429: Should be set if Micron parts are used for the BIOS SPI chip
I'd like to understand more about this option. […]
Clarified the wording.
https://review.coreboot.org/c/coreboot/+/42567/8/src/soc/amd/picasso/Kconfig... PS8, Line 435: are always be used
"may always be used?"
Done
Matt Papageorge has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42567 )
Change subject: soc/amd/picasso: Populate EFS SPI values from Kconfig options ......................................................................
Set Ready For Review
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42567 )
Change subject: soc/amd/picasso: Populate EFS SPI values from Kconfig options ......................................................................
Patch Set 11:
(2 comments)
https://review.coreboot.org/c/coreboot/+/42567/11/src/mainboard/amd/mandolin... File src/mainboard/amd/mandolin/Kconfig:
https://review.coreboot.org/c/coreboot/+/42567/11/src/mainboard/amd/mandolin... PS11, Line 13: select DEFAULT_SPI_READ_MODE_NORMAL_66M My impression is still that normal mode reads, without dummy cycles, are rarely or never supported with >50MHz frequencies.
https://review.coreboot.org/c/coreboot/+/42567/11/src/soc/amd/picasso/Kconfi... File src/soc/amd/picasso/Kconfig:
https://review.coreboot.org/c/coreboot/+/42567/11/src/soc/amd/picasso/Kconfi... PS11, Line 471: default 1 if SPI_MICRON_ALWAYS amdfwtool also has case 2 ?
Matt Papageorge has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42567 )
Change subject: soc/amd/picasso: Populate EFS SPI values from Kconfig options ......................................................................
Patch Set 11:
(2 comments)
https://review.coreboot.org/c/coreboot/+/42567/11/src/mainboard/amd/mandolin... File src/mainboard/amd/mandolin/Kconfig:
https://review.coreboot.org/c/coreboot/+/42567/11/src/mainboard/amd/mandolin... PS11, Line 13: select DEFAULT_SPI_READ_MODE_NORMAL_66M
My impression is still that normal mode reads, without dummy cycles, are rarely or never supported w […]
Will have to check on this
https://review.coreboot.org/c/coreboot/+/42567/11/src/soc/amd/picasso/Kconfi... File src/soc/amd/picasso/Kconfig:
https://review.coreboot.org/c/coreboot/+/42567/11/src/soc/amd/picasso/Kconfi... PS11, Line 471: default 1 if SPI_MICRON_ALWAYS
amdfwtool also has case 2 ?
This is for Renoir and other future processors
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42567 )
Change subject: soc/amd/picasso: Populate EFS SPI values from Kconfig options ......................................................................
Patch Set 11:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42567/11/src/soc/amd/picasso/Kconfi... File src/soc/amd/picasso/Kconfig:
https://review.coreboot.org/c/coreboot/+/42567/11/src/soc/amd/picasso/Kconfi... PS11, Line 471: default 1 if SPI_MICRON_ALWAYS
This is for Renoir and other future processors
Why are these placed in amd/picasso and not amd/common? And since everything depends of the BOM nothing should appear as a visible option in menuconfig.
Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42567 )
Change subject: soc/amd/picasso: Populate EFS SPI values from Kconfig options ......................................................................
Patch Set 11:
(5 comments)
https://review.coreboot.org/c/coreboot/+/42567/11/src/soc/amd/picasso/Kconfi... File src/soc/amd/picasso/Kconfig:
https://review.coreboot.org/c/coreboot/+/42567/11/src/soc/amd/picasso/Kconfi... PS11, Line 379: default SPI_READ_MODE_DUAL_IO_112 if DEFAULT_SPI_READ_MODE_DUAL_IO_112 If you want the default default to be 112, leave off the "if statement". Kconfig will select the first value in the choice list below (NORMAL_33M) as the default if there's no other default selected.
https://review.coreboot.org/c/coreboot/+/42567/11/src/soc/amd/picasso/Kconfi... PS11, Line 381: numbers numbers X-Y-Z values?
https://review.coreboot.org/c/coreboot/+/42567/11/src/soc/amd/picasso/Kconfi... PS11, Line 456: SPI_MICRON_ALWAYS So I'm still not certain of the actual impact of this. You probably also want to add a way to have the board select SPI_MICRON_NONE. Not being able to directly select the choices is a definite downside to the choice menus.
https://review.coreboot.org/c/coreboot/+/42567/11/src/soc/amd/picasso/Kconfi... PS11, Line 471: default 1 if SPI_MICRON_ALWAYS
Why are these placed in amd/picasso and not amd/common? And since everything depends of the BOM noth […]
I agree, this should probably go in the src/soc/amd/common/block/spi/Kconfig file.
https://review.coreboot.org/c/coreboot/+/42567/11/src/soc/amd/picasso/Makefi... File src/soc/amd/picasso/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/42567/11/src/soc/amd/picasso/Makefi... PS11, Line 379: --soc-name "Picasso" Does this apply for Pollock and Dali as well?
Hello build bot (Jenkins), Raul Rangel, Martin Roth, Furquan Shaikh, Patrick Georgi, Marshall Dawson, Nikolai Vyssotski, Aaron Durbin, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42567
to look at the new patch set (#12).
Change subject: soc/amd/picasso: Populate EFS SPI values from Kconfig options ......................................................................
soc/amd/picasso: Populate EFS SPI values from Kconfig options
The Embedded Firmware Structure should contain various SPI parameters for the PSP to program. This information is currently only programmed at run-time. This change is to populate them at build time as well.
BUG=b:158755102 TEST=Read EFS values at appropriate offsets using a hex editor. Boot test on Tremblye and Morphius. Select various boards in kconfig to make sure the defaults are loaded properly.
Signed-off-by: Matt Papageorge matt.papageorge@amd.corp-partner.google.com Change-Id: I78558fa3fa27c70820f0f3d636544127adab6f8b --- M src/mainboard/amd/mandolin/Kconfig M src/soc/amd/common/block/spi/Kconfig M src/soc/amd/picasso/Makefile.inc 3 files changed, 53 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/42567/12
Hello build bot (Jenkins), Raul Rangel, Martin Roth, Furquan Shaikh, Patrick Georgi, Marshall Dawson, Nikolai Vyssotski, Aaron Durbin, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42567
to look at the new patch set (#13).
Change subject: soc/amd/picasso: Populate EFS SPI values from Kconfig options ......................................................................
soc/amd/picasso: Populate EFS SPI values from Kconfig options
The Embedded Firmware Structure should contain various SPI parameters for the PSP to program. This information is currently only programmed at run-time. This change is to populate them at build time as well.
BUG=b:158755102 TEST=Read EFS values at appropriate offsets using a hex editor. Boot test on Tremblye and Morphius. Select various boards in kconfig to make sure the defaults are loaded properly.
Signed-off-by: Matt Papageorge matt.papageorge@amd.corp-partner.google.com Change-Id: I78558fa3fa27c70820f0f3d636544127adab6f8b --- M src/mainboard/amd/mandolin/Kconfig M src/soc/amd/common/block/spi/Kconfig M src/soc/amd/picasso/Makefile.inc 3 files changed, 53 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/42567/13
Matt Papageorge has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42567 )
Change subject: soc/amd/picasso: Populate EFS SPI values from Kconfig options ......................................................................
Patch Set 13:
(9 comments)
https://review.coreboot.org/c/coreboot/+/42567/7/src/soc/amd/picasso/Kconfig File src/soc/amd/picasso/Kconfig:
https://review.coreboot.org/c/coreboot/+/42567/7/src/soc/amd/picasso/Kconfig... PS7, Line 373: default SPI_READ_MODE_NORMAL_66M if BOARD_AMD_MANDOLIN
Tried this, unfortunately I cannot 'select' an option from a 'choice' statement. […]
Done
https://review.coreboot.org/c/coreboot/+/42567/8/src/soc/amd/picasso/Kconfig File src/soc/amd/picasso/Kconfig:
https://review.coreboot.org/c/coreboot/+/42567/8/src/soc/amd/picasso/Kconfig... PS8, Line 391: "Normal Read (up to 66M)"
I need to get answers to this
Still trying to get answers for this in b/158755102 #14. Should we hold the change for this?
https://review.coreboot.org/c/coreboot/+/42567/11/src/soc/amd/picasso/Kconfi... File src/soc/amd/picasso/Kconfig:
https://review.coreboot.org/c/coreboot/+/42567/11/src/soc/amd/picasso/Kconfi... PS11, Line 379: default SPI_READ_MODE_DUAL_IO_112 if DEFAULT_SPI_READ_MODE_DUAL_IO_112
If you want the default default to be 112, leave off the "if statement". […]
Ack
https://review.coreboot.org/c/coreboot/+/42567/11/src/soc/amd/picasso/Kconfi... PS11, Line 381: numbers numbers
X-Y-Z values?
Ack
https://review.coreboot.org/c/coreboot/+/42567/11/src/soc/amd/picasso/Kconfi... PS11, Line 456: SPI_MICRON_ALWAYS
So I'm still not certain of the actual impact of this. […]
Ack
https://review.coreboot.org/c/coreboot/+/42567/11/src/soc/amd/picasso/Kconfi... PS11, Line 471: default 1 if SPI_MICRON_ALWAYS
I agree, this should probably go in the src/soc/amd/common/block/spi/Kconfig file.
Done
https://review.coreboot.org/c/coreboot/+/42567/8/src/soc/amd/picasso/Makefil... File src/soc/amd/picasso/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/42567/8/src/soc/amd/picasso/Makefil... PS8, Line 326: EFS_SPI_READ_MODE=0
Why not do all of these in the Kconfig instead of in the makefile?
Done
https://review.coreboot.org/c/coreboot/+/42567/8/src/soc/amd/picasso/Makefil... PS8, Line 340: EFS_SPI_READ_MODE
If you put all of that in the Kconfig file, you can just use CONFIG_EFS_SPI_READ_MODE here.
Done
https://review.coreboot.org/c/coreboot/+/42567/11/src/soc/amd/picasso/Makefi... File src/soc/amd/picasso/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/42567/11/src/soc/amd/picasso/Makefi... PS11, Line 379: --soc-name "Picasso"
Does this apply for Pollock and Dali as well?
Yes, but only "Picasso" and "Raven" name strings are supported.
Originally I had parameters for passing in target family and model which would have been more explicit and better line up with what is used in the EFS spec. But feedback from the amdfw change indicated a strong preference for passing in the SOC name instead. For AMD kicker products like Pollock/Dali the main product name should be passed in.
Hello build bot (Jenkins), Raul Rangel, Martin Roth, Furquan Shaikh, Patrick Georgi, Marshall Dawson, Nikolai Vyssotski, Aaron Durbin, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42567
to look at the new patch set (#14).
Change subject: soc/amd/picasso: Populate EFS SPI values from Kconfig options ......................................................................
soc/amd/picasso: Populate EFS SPI values from Kconfig options
The Embedded Firmware Structure should contain various SPI parameters for the PSP to program. This information is currently only programmed at run-time. This change is to populate them at build time as well.
BUG=b:158755102 TEST=Read EFS values at appropriate offsets using a hex editor. Boot test on Tremblye and Morphius. Select various boards in kconfig to make sure the defaults are loaded properly.
Signed-off-by: Matt Papageorge matt.papageorge@amd.corp-partner.google.com Change-Id: I78558fa3fa27c70820f0f3d636544127adab6f8b --- M src/mainboard/amd/mandolin/Kconfig M src/soc/amd/common/block/spi/Kconfig M src/soc/amd/picasso/Makefile.inc 3 files changed, 54 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/42567/14
Matt Papageorge has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42567 )
Change subject: amd/common/block/spi: Add EFS SPI configurations to Kconfig ......................................................................
Patch Set 17:
I have refactored the change as follows. 1. Kconfig changes 2. Build changes for picasso platforms 3. Build changes for stoney ridge platforms
An optional future 4th change would be to address the duplicate definition of this information in mainboard/google/kahlee/bootblock/bootblock.c mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb
Matt Papageorge has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42567 )
Change subject: amd/common/block/spi: Add EFS SPI configurations to Kconfig ......................................................................
Patch Set 17:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42567/2/src/soc/amd/picasso/Kconfig File src/soc/amd/picasso/Kconfig:
https://review.coreboot.org/c/coreboot/+/42567/2/src/soc/amd/picasso/Kconfig... PS2, Line 373: value common_config.spi_config
next revision I will add another patch at the end of this chain to accomplish this
Attempting to do this caused lots of potential issues. Right now I am planning on a 4th patch in this stack to accomplish this independently of adding EFS support
Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42567 )
Change subject: amd/common/block/spi: Add EFS SPI configurations to Kconfig ......................................................................
Patch Set 17:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42567/2/src/soc/amd/picasso/Kconfig File src/soc/amd/picasso/Kconfig:
https://review.coreboot.org/c/coreboot/+/42567/2/src/soc/amd/picasso/Kconfig... PS2, Line 373: value common_config.spi_config
next revision I will add another patch at the end of this chain to accomplish this
Going to resolve for now so it can be merged.
Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42567 )
Change subject: amd/common/block/spi: Add EFS SPI configurations to Kconfig ......................................................................
Patch Set 17: Code-Review+2
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42567 )
Change subject: amd/common/block/spi: Add EFS SPI configurations to Kconfig ......................................................................
Patch Set 17: Code-Review+1
(3 comments)
https://review.coreboot.org/c/coreboot/+/42567/17/src/soc/amd/common/block/s... File src/soc/amd/common/block/spi/Kconfig:
https://review.coreboot.org/c/coreboot/+/42567/17/src/soc/amd/common/block/s... PS17, Line 15: range 0 7 nit: default 0 if EM100
https://review.coreboot.org/c/coreboot/+/42567/17/src/soc/amd/common/block/s... PS17, Line 33: range 0 5 default 3 if EM100
https://review.coreboot.org/c/coreboot/+/42567/7/src/soc/amd/picasso/Kconfig File src/soc/amd/picasso/Kconfig:
https://review.coreboot.org/c/coreboot/+/42567/7/src/soc/amd/picasso/Kconfig... PS7, Line 373: BOARD_AMD_MANDOLIN Why does SoC code have mainboard specific checks? This shouldn't be here.
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42567 )
Change subject: amd/common/block/spi: Add EFS SPI configurations to Kconfig ......................................................................
Patch Set 17:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42567/7/src/soc/amd/picasso/Kconfig File src/soc/amd/picasso/Kconfig:
https://review.coreboot.org/c/coreboot/+/42567/7/src/soc/amd/picasso/Kconfig... PS7, Line 373: BOARD_AMD_MANDOLIN
Why does SoC code have mainboard specific checks? This shouldn't be here.
Please ignore. Stale comment on older patchset.
Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42567 )
Change subject: amd/common/block/spi: Add EFS SPI configurations to Kconfig ......................................................................
Patch Set 17:
(2 comments)
https://review.coreboot.org/c/coreboot/+/42567/17/src/soc/amd/common/block/s... File src/soc/amd/common/block/spi/Kconfig:
https://review.coreboot.org/c/coreboot/+/42567/17/src/soc/amd/common/block/s... PS17, Line 15: range 0 7
nit: default 0 if EM100
Why are you looking to change the EM100 setting here? EM100 on zork support 2 and 4.
https://review.coreboot.org/c/coreboot/+/42567/17/src/soc/amd/common/block/s... PS17, Line 33: range 0 5
default 3 if EM100
This is only a zork limitation isn't it? I'm sure that other boards could support a faster speed since they wouldn't use the yoshi cable. I think we should leave the EM100 settings in the zork Kconfig.
Thoughts?
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42567 )
Change subject: amd/common/block/spi: Add EFS SPI configurations to Kconfig ......................................................................
Patch Set 17:
(2 comments)
https://review.coreboot.org/c/coreboot/+/42567/17/src/soc/amd/common/block/s... File src/soc/amd/common/block/spi/Kconfig:
https://review.coreboot.org/c/coreboot/+/42567/17/src/soc/amd/common/block/s... PS17, Line 15: range 0 7
Why are you looking to change the EM100 setting here? EM100 on zork support 2 and 4.
To keep it in sync with fch_spi_config_em100_modes: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/master:src/th...
https://review.coreboot.org/c/coreboot/+/42567/17/src/soc/amd/common/block/s... PS17, Line 33: range 0 5
This is only a zork limitation isn't it? I'm sure that other boards could support a faster speed sin […]
I was intending to keep it in sync with the implementation that existed in the spi driver to fch_spi_config_em100_modes(). Most devices I have worked on have required slower SPI speeds for em100, but all of them also had yoshi cables. So, probably it is not a problem for other boards. We can keep it in zork. I saw that it was being enabled for mandolin as well. Hence, the comment.
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42567 )
Change subject: amd/common/block/spi: Add EFS SPI configurations to Kconfig ......................................................................
Patch Set 17:
(2 comments)
https://review.coreboot.org/c/coreboot/+/42567/17/src/soc/amd/common/block/s... File src/soc/amd/common/block/spi/Kconfig:
https://review.coreboot.org/c/coreboot/+/42567/17/src/soc/amd/common/block/s... PS17, Line 15: range 0 7
To keep it in sync with fch_spi_config_em100_modes: https://source.chromium. […]
em100 supports fast read. the problem with the em100 is mostly in normal read with higher frequencies; fast read adds a dummy byte after the address and before the data transfer which massively relaxes the internal latency requirement
https://review.coreboot.org/c/coreboot/+/42567/17/src/soc/amd/common/block/s... PS17, Line 33: range 0 5
I was intending to keep it in sync with the implementation that existed in the spi driver to fch_spi […]
IIRC it generally needs to be at most 33MHz, but for zork devices the maximum frequency was lower due to longer cables. the default of 66MHz will probably break general EM100 support
Matt Papageorge has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42567 )
Change subject: amd/common/block/spi: Add EFS SPI configurations to Kconfig ......................................................................
Patch Set 17:
(2 comments)
https://review.coreboot.org/c/coreboot/+/42567/17/src/soc/amd/common/block/s... File src/soc/amd/common/block/spi/Kconfig:
https://review.coreboot.org/c/coreboot/+/42567/17/src/soc/amd/common/block/s... PS17, Line 15: range 0 7
em100 supports fast read. […]
See other reply. Feel free to open if you disagree.
https://review.coreboot.org/c/coreboot/+/42567/17/src/soc/amd/common/block/s... PS17, Line 33: range 0 5
IIRC it generally needs to be at most 33MHz, but for zork devices the maximum frequency was lower du […]
I explicitly specified it in both Mandolin and Zork rather than relying on the default to remove any ambiguity. This will be useful when/if we refactor out the fast speed and mode from the device tree and use kconfig on a per-platform basis. Anyone browsing the code will be able to more easily determine the platform SPI speed without having to browse to the common kconfig.
Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42567 )
Change subject: amd/common/block/spi: Add EFS SPI configurations to Kconfig ......................................................................
Patch Set 17:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42567/17/src/soc/amd/common/block/s... File src/soc/amd/common/block/spi/Kconfig:
https://review.coreboot.org/c/coreboot/+/42567/17/src/soc/amd/common/block/s... PS17, Line 33: range 0 5
I explicitly specified it in both Mandolin and Zork rather than relying on the default to remove any […]
I'm planning on reworking the EM100 code. There are now two different versions that support different speeds. I'd ask that we go ahead and merget this for now, and I'll get it updated shortly. I can file a bug to do that and assign it to myself.
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42567 )
Change subject: amd/common/block/spi: Add EFS SPI configurations to Kconfig ......................................................................
Patch Set 17:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42567/17/src/soc/amd/common/block/s... File src/soc/amd/common/block/spi/Kconfig:
https://review.coreboot.org/c/coreboot/+/42567/17/src/soc/amd/common/block/s... PS17, Line 33: range 0 5
I'm planning on reworking the EM100 code. […]
SG.
Furquan Shaikh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/42567 )
Change subject: amd/common/block/spi: Add EFS SPI configurations to Kconfig ......................................................................
amd/common/block/spi: Add EFS SPI configurations to Kconfig
The Embedded Firmware Structure should contain SPI speed, mode and Micron support for the PSP to program. Add Kconfig options to specify these values to use for future platform changes.
BUG=b:158755102 TEST=Test menuconfig and platform build for Trembyle and Mandolin.
Signed-off-by: Matt Papageorge matt.papageorge@amd.corp-partner.google.com Change-Id: I78558fa3fa27c70820f0f3d636544127adab6f8b Reviewed-on: https://review.coreboot.org/c/coreboot/+/42567 Reviewed-by: Raul Rangel rrangel@chromium.org Reviewed-by: Martin Roth martinroth@google.com Reviewed-by: Furquan Shaikh furquan@google.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/amd/common/block/spi/Kconfig 1 file changed, 43 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved Furquan Shaikh: Looks good to me, but someone else must approve Raul Rangel: Looks good to me, approved
diff --git a/src/soc/amd/common/block/spi/Kconfig b/src/soc/amd/common/block/spi/Kconfig index 785e6da..c8f6d1e 100644 --- a/src/soc/amd/common/block/spi/Kconfig +++ b/src/soc/amd/common/block/spi/Kconfig @@ -9,3 +9,46 @@ config SOC_AMD_COMMON_BLOCK_SPI_DEBUG bool default n + +config EFS_SPI_READ_MODE + int + range 0 7 + default 2 + help + SPI read mode to be programmed by the PSP. + The numbers in the options below indicate how many wires + are utilized for command, address and data. For instance 1-1-2 + means 1 command, 1 address and 2 data wires. + 0: Normal Read (up to 33M) + 1: Reserved + 2: Dual IO (1-1-2) + 3: Quad IO (1-1-4) + 4: Dual IO (1-2-2) + 5: Quad IO (1-4-4) + 6: Normal Read (up to 66M) + 7: Fast Read + +config EFS_SPI_SPEED + int + range 0 5 + default 0 + help + SPI Fast Speed to be programmed by the PSP. + 0: 66.66Mhz + 1: 33.33MHz + 2: 22.22MHz + 3: 16.66MHz + 4: 100MHz + 5: 800KHz + +config EFS_SPI_MICRON_FLAG + int + range 0 2 + default 0 + help + For Family 17h Model 00h and later SoC the PSP must be aware if a Micron + part is present in EFS. Automatic detection (option 2) is available + for Family 17h Model 30h-3Fh but is unsupported otherwise. + 0: Board does not use Micron parts + 1: Board always uses Micron parts + 2: Micron parts are optional