Shelley Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32794
Change subject: mv/google/hatch: Set FSP SPI CS options ......................................................................
mv/google/hatch: Set FSP SPI CS options
Explicitly set SPI CS options in overridetree for kohaku and hatch.
BUG=b:130329260 BRANCH=None TEST=Boot up and make sure SPI CS options are set properly in fsp_params
Change-Id: Icbbab7df05ac38918ffd5c2d66d22d5db57d471b Signed-off-by: Shelley Chen shchen@google.com --- M src/mainboard/google/hatch/variants/hatch/overridetree.cb M src/mainboard/google/hatch/variants/kohaku/overridetree.cb 2 files changed, 22 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/32794/1
diff --git a/src/mainboard/google/hatch/variants/hatch/overridetree.cb b/src/mainboard/google/hatch/variants/hatch/overridetree.cb index 42752e6..4cb7fc9 100644 --- a/src/mainboard/google/hatch/variants/hatch/overridetree.cb +++ b/src/mainboard/google/hatch/variants/hatch/overridetree.cb @@ -15,6 +15,17 @@ [PchSerialIoIndexUART2] = PchSerialIoDisabled, }"
+ register "SerialIoSpi0CsPolarity[0]" = "0" + register "SerialIoSpi0CsPolarity[1]" = "0" + register "SerialIoSpi1CsPolarity[0]" = "0" + register "SerialIoSpi1CsPolarity[1]" = "0" + register "SerialIoSpi0CsEnable[0]" = "1" + register "SerialIoSpi0CsEnable[1]" = "0" + register "SerialIoSpi1CsEnable[0]" = "0" + register "SerialIoSpi1CsEnable[1]" = "1" + register "SerialIoSpiDefaultCsOutput[0]" = "0" + register "SerialIoSpiDefaultCsOutput[1]" = "1" + # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | diff --git a/src/mainboard/google/hatch/variants/kohaku/overridetree.cb b/src/mainboard/google/hatch/variants/kohaku/overridetree.cb index 9546420..4d7ba72 100644 --- a/src/mainboard/google/hatch/variants/kohaku/overridetree.cb +++ b/src/mainboard/google/hatch/variants/kohaku/overridetree.cb @@ -14,6 +14,17 @@ [PchSerialIoIndexUART2] = PchSerialIoDisabled, }"
+ register "SerialIoSpi0CsPolarity[0]" = "0" + register "SerialIoSpi0CsPolarity[1]" = "0" + register "SerialIoSpi1CsPolarity[0]" = "0" + register "SerialIoSpi1CsPolarity[1]" = "0" + register "SerialIoSpi0CsEnable[0]" = "1" + register "SerialIoSpi0CsEnable[1]" = "0" + register "SerialIoSpi1CsEnable[0]" = "0" + register "SerialIoSpi1CsEnable[1]" = "1" + register "SerialIoSpiDefaultCsOutput[0]" = "0" + register "SerialIoSpiDefaultCsOutput[1]" = "1" + # No PCIe WiFi register "PcieRpEnable[13]" = "0"
Paul Fagerburg has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32794 )
Change subject: mv/google/hatch: Set FSP SPI CS options ......................................................................
Patch Set 1: Code-Review+1
(1 comment)
https://review.coreboot.org/#/c/32794/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/32794/1//COMMIT_MSG@7 PS1, Line 7: mv/google/hatch: Set FSP SPI CS options mb, not mv?
Shelley Chen has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/32794 )
Change subject: mv/google/hatch: Set FSP SPI CS options ......................................................................
Abandoned
-
Paul Fagerburg (Code Review) -
Shelley Chen (Code Review)