Saurabh Mishra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81850?usp=email )
Change subject: soc/intel/common: Add Lunar Lake IAA & OSSE device IDs ......................................................................
soc/intel/common: Add Lunar Lake IAA & OSSE device IDs
Reference: Lunar Lake External Design Specification Volume 1 (734362)
Change-Id: I92b65c946682387cbb841d558c6f0a7cb0fcd4ac Signed-off-by: Saurabh Mishra mishra.saurabh@intel.com --- M src/include/device/pci_ids.h 1 file changed, 9 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/81850/1
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 5f7c178..8e1c876 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -4678,6 +4678,7 @@ #define PCI_DID_INTEL_LNL_TBT_RP0 0xa84e #define PCI_DID_INTEL_LNL_TBT_RP1 0xa84f #define PCI_DID_INTEL_LNL_TBT_RP2 0xa860 +#define PCI_DID_INTEL_LNL_TBT_RP3 0xa837 #define PCI_DID_INTEL_LNL_TBT_DMA0 0xa833 #define PCI_DID_INTEL_LNL_TBT_DMA1 0xa834 #define PCI_DID_INTEL_PTL_TBT_DMA0 0xE433 @@ -4794,6 +4795,14 @@ #define PCI_DID_INTEL_LNL_PSE1 0xa863 #define PCI_DID_INTEL_LNL_PSE2 0xa864
+/* In-memory Analytics Accelerator device IDs */ +#define PCI_DID_INTEL_LNL_IAA 0x642d + +/* OS Security Engine */ +#define PCI_DID_INTEL_LNL_OSSE0 0xa862 +#define PCI_DID_INTEL_LNL_OSSE1 0xa863 +#define PCI_DID_INTEL_LNL_OSSE2 0xa864 + /* Intel Crashlog */ #define PCI_DID_INTEL_TGL_CPU_CRASHLOG_SRAM 0x9a0d #define PCI_DID_INTEL_ADL_CPU_CRASHLOG_SRAM 0x467d