David Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42276 )
Change subject: soc/intel/tigerlake: Configure CA Mirror ......................................................................
soc/intel/tigerlake: Configure CA Mirror
BUG=b:156435028 BRANCH=none TEST=FW_NAME=terrador emerge-volteer coreboot chromeos-bootimage
Signed-off-by: David Wu david_wu@quanta.corp-partner.google.com Change-Id: Idae9fa439f077f8f3fb16fe74c2f263c008cd5f4 --- M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/romstage/fsp_params.c 2 files changed, 6 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/42276/1
diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index e693699..2c7b604 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -83,6 +83,9 @@ /* Rank Margin Tool. 1:Enable, 0:Disable */ uint8_t RMT;
+ /* LPDDR4x Command Pins Mirrored */ + uint32_t CmdMirror; + /* USB related */ struct usb2_port_config usb2_ports[16]; struct usb3_port_config usb3_ports[10]; diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c index f7956c8..b77bb66 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params.c @@ -196,6 +196,9 @@
/* Change VmxEnable UPD value according to ENABLE_VMX Kconfig */ m_cfg->VmxEnable = CONFIG(ENABLE_VMX); + + /* LPDDR4x Command Pins Mirrored */ + m_cfg->CmdMirror[0] = config->CmdMirror; }
void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
Kane Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42276 )
Change subject: soc/intel/tigerlake: Configure CA Mirror ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42276/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/42276/1//COMMIT_MSG@7 PS1, Line 7: soc/intel/tigerlake: Configure CA Mirror soc/intel/tigerlake: Add CmdMirror option in chip.h
Provide CmdMirror option in chip.h so that it can control CmdMirror FSP UPD via dev tree.
Hello build bot (Jenkins), Furquan Shaikh, Kane Chen, Tim Wawrzynczak, Paul Fagerburg, Nick Vaccaro, Derek Huang, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42276
to look at the new patch set (#2).
Change subject: soc/intel/tigerlake: Add CmdMirror option in chip.h ......................................................................
soc/intel/tigerlake: Add CmdMirror option in chip.h
Provide CmdMirror option in chip.h so that it can control CmdMirror FSP UPD via dev tree.
BUG=b:156435028 BRANCH=none TEST=FW_NAME=terrador emerge-volteer coreboot chromeos-bootimage
Signed-off-by: David Wu david_wu@quanta.corp-partner.google.com Change-Id: Idae9fa439f077f8f3fb16fe74c2f263c008cd5f4 --- M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/romstage/fsp_params.c 2 files changed, 6 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/42276/2
David Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42276 )
Change subject: soc/intel/tigerlake: Add CmdMirror option in chip.h ......................................................................
Patch Set 2:
(1 comment)
Thanks.
https://review.coreboot.org/c/coreboot/+/42276/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/42276/1//COMMIT_MSG@7 PS1, Line 7: soc/intel/tigerlake: Configure CA Mirror
soc/intel/tigerlake: Add CmdMirror option in chip.h […]
Done
Paul Fagerburg has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42276 )
Change subject: soc/intel/tigerlake: Add CmdMirror option in chip.h ......................................................................
Patch Set 2: Code-Review+1
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42276 )
Change subject: soc/intel/tigerlake: Add CmdMirror option in chip.h ......................................................................
Patch Set 2:
(2 comments)
https://review.coreboot.org/c/coreboot/+/42276/2/src/soc/intel/tigerlake/chi... File src/soc/intel/tigerlake/chip.h:
https://review.coreboot.org/c/coreboot/+/42276/2/src/soc/intel/tigerlake/chi... PS2, Line 86: LPDDR4x I don't believe the mirroring is LPDDR4 specific.
https://review.coreboot.org/c/coreboot/+/42276/2/src/soc/intel/tigerlake/rom... File src/soc/intel/tigerlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/42276/2/src/soc/intel/tigerlake/rom... PS2, Line 200: LPDDR4x same
Hello build bot (Jenkins), Furquan Shaikh, Kane Chen, Tim Wawrzynczak, Paul Fagerburg, Nick Vaccaro, Derek Huang, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42276
to look at the new patch set (#3).
Change subject: soc/intel/tigerlake: Add CmdMirror option in chip.h ......................................................................
soc/intel/tigerlake: Add CmdMirror option in chip.h
Provide CmdMirror option in chip.h so that it can control CmdMirror FSP UPD via dev tree.
BUG=b:156435028 BRANCH=none TEST=FW_NAME=terrador emerge-volteer coreboot chromeos-bootimage
Signed-off-by: David Wu david_wu@quanta.corp-partner.google.com Change-Id: Idae9fa439f077f8f3fb16fe74c2f263c008cd5f4 --- M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/romstage/fsp_params.c 2 files changed, 6 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/42276/3
David Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42276 )
Change subject: soc/intel/tigerlake: Add CmdMirror option in chip.h ......................................................................
Patch Set 3:
(2 comments)
https://review.coreboot.org/c/coreboot/+/42276/2/src/soc/intel/tigerlake/chi... File src/soc/intel/tigerlake/chip.h:
https://review.coreboot.org/c/coreboot/+/42276/2/src/soc/intel/tigerlake/chi... PS2, Line 86: LPDDR4x
I don't believe the mirroring is LPDDR4 specific.
Removed.
https://review.coreboot.org/c/coreboot/+/42276/2/src/soc/intel/tigerlake/rom... File src/soc/intel/tigerlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/42276/2/src/soc/intel/tigerlake/rom... PS2, Line 200: LPDDR4x
same
Removed.
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42276 )
Change subject: soc/intel/tigerlake: Add CmdMirror option in chip.h ......................................................................
Patch Set 3: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/42276/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/42276/3//COMMIT_MSG@10 PS3, Line 10: it can control CmdMirror FSP UPD via dev tree. Please re-flow for 75 character line length.
Hello build bot (Jenkins), Furquan Shaikh, Kane Chen, Paul Menzel, Tim Wawrzynczak, Paul Fagerburg, Nick Vaccaro, Derek Huang, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42276
to look at the new patch set (#4).
Change subject: soc/intel/tigerlake: Add CmdMirror option in chip.h ......................................................................
soc/intel/tigerlake: Add CmdMirror option in chip.h
Provide CmdMirror option in chip.h so that it can control CmdMirror FSP UPD via dev tree.
BUG=b:156435028 BRANCH=none TEST=FW_NAME=terrador emerge-volteer coreboot chromeos-bootimage
Signed-off-by: David Wu david_wu@quanta.corp-partner.google.com Change-Id: Idae9fa439f077f8f3fb16fe74c2f263c008cd5f4 --- M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/romstage/fsp_params.c 2 files changed, 6 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/42276/4
David Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42276 )
Change subject: soc/intel/tigerlake: Add CmdMirror option in chip.h ......................................................................
Patch Set 4:
(1 comment)
Patch Set 2:
(2 comments)
https://review.coreboot.org/c/coreboot/+/42276/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/42276/3//COMMIT_MSG@10 PS3, Line 10: it can control CmdMirror FSP UPD via dev tree.
Please re-flow for 75 character line length.
Done
Paul Fagerburg has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42276 )
Change subject: soc/intel/tigerlake: Add CmdMirror option in chip.h ......................................................................
Patch Set 5: Code-Review+1
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42276 )
Change subject: soc/intel/tigerlake: Add CmdMirror option in chip.h ......................................................................
Patch Set 5: Code-Review+2
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42276 )
Change subject: soc/intel/tigerlake: Add CmdMirror option in chip.h ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42276/5/src/soc/intel/tigerlake/chi... File src/soc/intel/tigerlake/chip.h:
https://review.coreboot.org/c/coreboot/+/42276/5/src/soc/intel/tigerlake/chi... PS5, Line 114: CmdMirror What are the expected values?
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42276 )
Change subject: soc/intel/tigerlake: Add CmdMirror option in chip.h ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42276/5/src/soc/intel/tigerlake/chi... File src/soc/intel/tigerlake/chip.h:
https://review.coreboot.org/c/coreboot/+/42276/5/src/soc/intel/tigerlake/chi... PS5, Line 114: CmdMirror
What are the expected values?
Check the UPD comments 😊
David Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42276 )
Change subject: soc/intel/tigerlake: Add CmdMirror option in chip.h ......................................................................
Patch Set 6: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/42276/5/src/soc/intel/tigerlake/chi... File src/soc/intel/tigerlake/chip.h:
https://review.coreboot.org/c/coreboot/+/42276/5/src/soc/intel/tigerlake/chi... PS5, Line 114: CmdMirror
Check the UPD comments 😊
Ack
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/42276 )
Change subject: soc/intel/tigerlake: Add CmdMirror option in chip.h ......................................................................
soc/intel/tigerlake: Add CmdMirror option in chip.h
Provide CmdMirror option in chip.h so that it can control CmdMirror FSP UPD via dev tree.
BUG=b:156435028 BRANCH=none TEST=FW_NAME=terrador emerge-volteer coreboot chromeos-bootimage
Signed-off-by: David Wu david_wu@quanta.corp-partner.google.com Change-Id: Idae9fa439f077f8f3fb16fe74c2f263c008cd5f4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42276 Reviewed-by: Paul Fagerburg pfagerburg@chromium.org Reviewed-by: Tim Wawrzynczak twawrzynczak@chromium.org Reviewed-by: Paul Menzel paulepanter@users.sourceforge.net Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/romstage/fsp_params.c 2 files changed, 6 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve David Wu: Looks good to me, but someone else must approve Tim Wawrzynczak: Looks good to me, approved Paul Fagerburg: Looks good to me, but someone else must approve
diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index 8b1fe2d..c72698f 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -115,6 +115,9 @@ /* Rank Margin Tool. 1:Enable, 0:Disable */ uint8_t RMT;
+ /* Command Pins Mirrored */ + uint32_t CmdMirror; + /* USB related */ struct usb2_port_config usb2_ports[16]; struct usb3_port_config usb3_ports[10]; diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c index f7956c8..1a46b7a 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params.c @@ -196,6 +196,9 @@
/* Change VmxEnable UPD value according to ENABLE_VMX Kconfig */ m_cfg->VmxEnable = CONFIG(ENABLE_VMX); + + /* Command Pins Mirrored */ + m_cfg->CmdMirror[0] = config->CmdMirror; }
void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
-
David Wu (Code Review) -
Furquan Shaikh (Code Review)
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Kane Chen (Code Review)
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Patrick Georgi (Code Review)
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Paul Fagerburg (Code Review)
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Paul Menzel (Code Review)
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Tim Wawrzynczak (Code Review)