David Wu has uploaded this change for review.

View Change

soc/intel/tigerlake: Configure CA Mirror

BUG=b:156435028
BRANCH=none
TEST=FW_NAME=terrador emerge-volteer coreboot chromeos-bootimage

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Idae9fa439f077f8f3fb16fe74c2f263c008cd5f4
---
M src/soc/intel/tigerlake/chip.h
M src/soc/intel/tigerlake/romstage/fsp_params.c
2 files changed, 6 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/42276/1

diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h
index e693699..2c7b604 100644
--- a/src/soc/intel/tigerlake/chip.h
+++ b/src/soc/intel/tigerlake/chip.h
@@ -83,6 +83,9 @@
 	/* Rank Margin Tool. 1:Enable, 0:Disable */
 	uint8_t RMT;
 
+	/* LPDDR4x Command Pins Mirrored */
+	uint32_t CmdMirror;
+
 	/* USB related */
 	struct usb2_port_config usb2_ports[16];
 	struct usb3_port_config usb3_ports[10];
diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c
index f7956c8..b77bb66 100644
--- a/src/soc/intel/tigerlake/romstage/fsp_params.c
+++ b/src/soc/intel/tigerlake/romstage/fsp_params.c
@@ -196,6 +196,9 @@
 
 	/* Change VmxEnable UPD value according to ENABLE_VMX Kconfig */
 	m_cfg->VmxEnable = CONFIG(ENABLE_VMX);
+
+	/* LPDDR4x Command Pins Mirrored */
+	m_cfg->CmdMirror[0] = config->CmdMirror;
 }
 
 void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)

To view, visit change 42276. To unsubscribe, or for help writing mail filters, visit settings.