Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44365 )
Change subject: soc/intel/skylake: Refactor ternary expressions ......................................................................
soc/intel/skylake: Refactor ternary expressions
Replace ternary expressions by `dev && dev->enabled`.
Change-Id: Ie7afa48bf2c8bdad5a043f7cb6953d05b7b6597d Signed-off-by: Felix Singer felixsinger@posteo.net --- M src/soc/intel/skylake/chip.c M src/soc/intel/skylake/romstage/romstage.c 2 files changed, 10 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/44365/1
diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index 9239fd2..e96d624 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -167,7 +167,7 @@ }
dev = pcidev_path_on_root(PCH_DEVFN_SATA); - params->SataEnable = dev ? dev->enabled : 0; + params->SataEnable = dev && dev->enabled; if (params->SataEnable) { memcpy(params->SataPortsEnable, config->SataPortsEnable, sizeof(params->SataPortsEnable)); @@ -236,7 +236,7 @@ params->SaImguEnable = dev && dev->enabled;
dev = pcidev_path_on_root(PCH_DEVFN_CSE_3); - params->Heci3Enabled = dev ? dev->enabled : 0; + params->Heci3Enabled = dev && dev->enabled;
params->LogoPtr = config->LogoPtr; params->LogoSize = config->LogoSize; @@ -248,7 +248,7 @@ params->PchPmLanWakeFromDeepSx = config->WakeConfigPcieWakeFromDeepSx;
dev = pcidev_path_on_root(PCH_DEVFN_GBE); - params->PchLanEnable = dev ? dev->enabled : 0; + params->PchLanEnable = dev && dev->enabled; if (params->PchLanEnable) { params->PchLanLtrEnable = config->EnableLanLtr; params->PchLanK1OffEnable = config->EnableLanK1Off; @@ -258,7 +258,7 @@ params->SsicPortEnable = config->SsicPortEnable;
dev = pcidev_path_on_root(PCH_DEVFN_EMMC); - params->ScsEmmcEnabled = dev ? dev->enabled : 0; + params->ScsEmmcEnabled = dev && dev->enabled; params->ScsEmmcHs400Enabled = config->ScsEmmcHs400Enabled;
dev = pcidev_path_on_root(PCH_DEVFN_SDCARD); @@ -275,10 +275,10 @@
/* If ISH is enabled, enable ISH elements */ dev = pcidev_path_on_root(PCH_DEVFN_ISH); - params->PchIshEnable = dev ? dev->enabled : 0; + params->PchIshEnable = dev && dev->enabled;
dev = pcidev_path_on_root(PCH_DEVFN_HDA); - params->PchHdaEnable = dev ? dev->enabled : 0; + params->PchHdaEnable = dev && dev->enabled;
params->PchHdaVcType = config->PchHdaVcType; params->PchHdaIoBufferOwnership = config->IoBufferOwnership; @@ -353,7 +353,7 @@
/* Show SPI controller if enabled in devicetree.cb */ dev = pcidev_path_on_root(PCH_DEVFN_SPI); - params->ShowSpiController = dev ? dev->enabled : 0; + params->ShowSpiController = dev && dev->enabled;
/* Enable xDCI controller if enabled in devicetree and allowed */ dev = pcidev_path_on_root(PCH_DEVFN_USBOTG); @@ -367,7 +367,7 @@
/* Enable or disable Gaussian Mixture Model in devicetree */ dev = pcidev_path_on_root(SA_DEVFN_GMM); - params->GmmEnable = dev ? dev->enabled : 0; + params->GmmEnable = dev && dev->enabled;
/* * Send VR specific mailbox commands: diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index 76f7a73..5d651ca 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -295,13 +295,13 @@ m_t_cfg->PchDciEn = config->PchDciEn;
dev = pcidev_path_on_root(PCH_DEVFN_TRACEHUB); - m_cfg->EnableTraceHub = dev ? dev->enabled : 0; + m_cfg->EnableTraceHub = dev && dev->enabled; m_cfg->TraceHubMemReg0Size = config->TraceHubMemReg0Size; m_cfg->TraceHubMemReg1Size = config->TraceHubMemReg1Size;
/* Enable SMBus controller */ dev = pcidev_path_on_root(PCH_DEVFN_SMBUS); - m_cfg->SmbusEnable = dev ? dev->enabled : 0; + m_cfg->SmbusEnable = dev && dev->enabled;
/* Set primary graphic device */ soc_primary_gfx_config_params(m_cfg, config);
Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/44365
to look at the new patch set (#2).
Change subject: soc/intel/skylake: Refactor ternary expressions ......................................................................
soc/intel/skylake: Refactor ternary expressions
To be consistent with the rest of the tree, replace all left ternary expressions, which are used for device enablement / disablement, by `dev && dev->enabled`.
Change-Id: Ie7afa48bf2c8bdad5a043f7cb6953d05b7b6597d Signed-off-by: Felix Singer felixsinger@posteo.net --- M src/soc/intel/skylake/chip.c M src/soc/intel/skylake/romstage/romstage.c 2 files changed, 10 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/44365/2
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44365 )
Change subject: soc/intel/skylake: Refactor ternary expressions ......................................................................
Patch Set 2: Code-Review+2
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44365 )
Change subject: soc/intel/skylake: Refactor ternary expressions ......................................................................
Patch Set 2:
Just curious, do the binaries change?
Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44365 )
Change subject: soc/intel/skylake: Refactor ternary expressions ......................................................................
Patch Set 2:
Patch Set 2:
Just curious, do the binaries change?
Just checked, built with BUILD_TIMELESS=1 and binary changed.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44365 )
Change subject: soc/intel/skylake: Refactor ternary expressions ......................................................................
Patch Set 3: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/44365/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/44365/3//COMMIT_MSG@11 PS3, Line 11: by replace *with*
Hello build bot (Jenkins), Angel Pons, Michael Niewöhner, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/44365
to look at the new patch set (#4).
Change subject: soc/intel/skylake: Refactor ternary expressions ......................................................................
soc/intel/skylake: Refactor ternary expressions
To be consistent with the rest of the tree, replace all left ternary expressions, which are used for device enablement / disablement, with `dev && dev->enabled`.
Change-Id: Ie7afa48bf2c8bdad5a043f7cb6953d05b7b6597d Signed-off-by: Felix Singer felixsinger@posteo.net --- M src/soc/intel/skylake/chip.c M src/soc/intel/skylake/romstage/romstage.c 2 files changed, 10 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/44365/4
Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44365 )
Change subject: soc/intel/skylake: Refactor ternary expressions ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/44365/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/44365/3//COMMIT_MSG@11 PS3, Line 11: by
replace *with*
Done
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44365 )
Change subject: soc/intel/skylake: Refactor ternary expressions ......................................................................
Patch Set 4: Code-Review+2
Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/44365 )
Change subject: soc/intel/skylake: Refactor ternary expressions ......................................................................
soc/intel/skylake: Refactor ternary expressions
To be consistent with the rest of the tree, replace all left ternary expressions, which are used for device enablement / disablement, with `dev && dev->enabled`.
Change-Id: Ie7afa48bf2c8bdad5a043f7cb6953d05b7b6597d Signed-off-by: Felix Singer felixsinger@posteo.net Reviewed-on: https://review.coreboot.org/c/coreboot/+/44365 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Michael Niewöhner --- M src/soc/intel/skylake/chip.c M src/soc/intel/skylake/romstage/romstage.c 2 files changed, 10 insertions(+), 10 deletions(-)
Approvals: build bot (Jenkins): Verified Michael Niewöhner: Looks good to me, approved
diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index 9239fd2..e96d624 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -167,7 +167,7 @@ }
dev = pcidev_path_on_root(PCH_DEVFN_SATA); - params->SataEnable = dev ? dev->enabled : 0; + params->SataEnable = dev && dev->enabled; if (params->SataEnable) { memcpy(params->SataPortsEnable, config->SataPortsEnable, sizeof(params->SataPortsEnable)); @@ -236,7 +236,7 @@ params->SaImguEnable = dev && dev->enabled;
dev = pcidev_path_on_root(PCH_DEVFN_CSE_3); - params->Heci3Enabled = dev ? dev->enabled : 0; + params->Heci3Enabled = dev && dev->enabled;
params->LogoPtr = config->LogoPtr; params->LogoSize = config->LogoSize; @@ -248,7 +248,7 @@ params->PchPmLanWakeFromDeepSx = config->WakeConfigPcieWakeFromDeepSx;
dev = pcidev_path_on_root(PCH_DEVFN_GBE); - params->PchLanEnable = dev ? dev->enabled : 0; + params->PchLanEnable = dev && dev->enabled; if (params->PchLanEnable) { params->PchLanLtrEnable = config->EnableLanLtr; params->PchLanK1OffEnable = config->EnableLanK1Off; @@ -258,7 +258,7 @@ params->SsicPortEnable = config->SsicPortEnable;
dev = pcidev_path_on_root(PCH_DEVFN_EMMC); - params->ScsEmmcEnabled = dev ? dev->enabled : 0; + params->ScsEmmcEnabled = dev && dev->enabled; params->ScsEmmcHs400Enabled = config->ScsEmmcHs400Enabled;
dev = pcidev_path_on_root(PCH_DEVFN_SDCARD); @@ -275,10 +275,10 @@
/* If ISH is enabled, enable ISH elements */ dev = pcidev_path_on_root(PCH_DEVFN_ISH); - params->PchIshEnable = dev ? dev->enabled : 0; + params->PchIshEnable = dev && dev->enabled;
dev = pcidev_path_on_root(PCH_DEVFN_HDA); - params->PchHdaEnable = dev ? dev->enabled : 0; + params->PchHdaEnable = dev && dev->enabled;
params->PchHdaVcType = config->PchHdaVcType; params->PchHdaIoBufferOwnership = config->IoBufferOwnership; @@ -353,7 +353,7 @@
/* Show SPI controller if enabled in devicetree.cb */ dev = pcidev_path_on_root(PCH_DEVFN_SPI); - params->ShowSpiController = dev ? dev->enabled : 0; + params->ShowSpiController = dev && dev->enabled;
/* Enable xDCI controller if enabled in devicetree and allowed */ dev = pcidev_path_on_root(PCH_DEVFN_USBOTG); @@ -367,7 +367,7 @@
/* Enable or disable Gaussian Mixture Model in devicetree */ dev = pcidev_path_on_root(SA_DEVFN_GMM); - params->GmmEnable = dev ? dev->enabled : 0; + params->GmmEnable = dev && dev->enabled;
/* * Send VR specific mailbox commands: diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index 76f7a73..5d651ca 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -295,13 +295,13 @@ m_t_cfg->PchDciEn = config->PchDciEn;
dev = pcidev_path_on_root(PCH_DEVFN_TRACEHUB); - m_cfg->EnableTraceHub = dev ? dev->enabled : 0; + m_cfg->EnableTraceHub = dev && dev->enabled; m_cfg->TraceHubMemReg0Size = config->TraceHubMemReg0Size; m_cfg->TraceHubMemReg1Size = config->TraceHubMemReg1Size;
/* Enable SMBus controller */ dev = pcidev_path_on_root(PCH_DEVFN_SMBUS); - m_cfg->SmbusEnable = dev ? dev->enabled : 0; + m_cfg->SmbusEnable = dev && dev->enabled;
/* Set primary graphic device */ soc_primary_gfx_config_params(m_cfg, config);
-
Angel Pons (Code Review) -
Felix Singer (Code Review)
-
Michael Niewöhner (Code Review)
-
Paul Menzel (Code Review)