Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/51002 )
Change subject: soc/intel/{adl,jsl,ehl,tgl}: Remove ITSS polarity restore ......................................................................
soc/intel/{adl,jsl,ehl,tgl}: Remove ITSS polarity restore
Post boot SAI PCR access to ITSS polarity regsiter is locked. Restore of ITSS polarity does not take effect anyways. Hence removing the related programming.
Change-Id: I1adab45ee903b9d9c1d98a060143445c0cee0968 Signed-off-by: Aamir Bohra aamir.bohra@intel.com --- M src/soc/intel/alderlake/chip.c M src/soc/intel/elkhartlake/chip.c M src/soc/intel/jasperlake/chip.c M src/soc/intel/tigerlake/chip.c 4 files changed, 0 insertions(+), 29 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/51002/1
diff --git a/src/soc/intel/alderlake/chip.c b/src/soc/intel/alderlake/chip.c index 95ad865..9777052 100644 --- a/src/soc/intel/alderlake/chip.c +++ b/src/soc/intel/alderlake/chip.c @@ -127,20 +127,12 @@
void soc_init_pre_device(void *chip_info) { - /* TODO: A bug has been filed, remove this W/A once FSP is updated */ - /* Snapshot the current GPIO IRQ polarities. FSP is setting a - * default policy that doesn't honor boards' requirements. */ - itss_snapshot_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); - /* Perform silicon specific init. */ fsp_silicon_init();
/* Display FIRMWARE_VERSION_INFO_HOB */ fsp_display_fvi_version_hob();
- /* Restore GPIO IRQ polarities back to previous settings. */ - itss_restore_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); - soc_fill_gpio_pm_configuration();
/* Swap enabled PCI ports in device tree if needed. */ diff --git a/src/soc/intel/elkhartlake/chip.c b/src/soc/intel/elkhartlake/chip.c index 001a6e1..f1c75b6 100644 --- a/src/soc/intel/elkhartlake/chip.c +++ b/src/soc/intel/elkhartlake/chip.c @@ -116,19 +116,12 @@
void soc_init_pre_device(void *chip_info) { - /* Snapshot the current GPIO IRQ polarities. FSP is setting a - * default policy that doesn't honor boards' requirements. */ - itss_snapshot_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); - /* Perform silicon specific init. */ fsp_silicon_init();
/* Display FIRMWARE_VERSION_INFO_HOB */ fsp_display_fvi_version_hob();
- /* Restore GPIO IRQ polarities back to previous settings. */ - itss_restore_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); - soc_fill_gpio_pm_configuration();
/* swap enabled PCI ports in device tree if needed */ diff --git a/src/soc/intel/jasperlake/chip.c b/src/soc/intel/jasperlake/chip.c index ce4004d..c663d1f 100644 --- a/src/soc/intel/jasperlake/chip.c +++ b/src/soc/intel/jasperlake/chip.c @@ -122,19 +122,12 @@
void soc_init_pre_device(void *chip_info) { - /* Snapshot the current GPIO IRQ polarities. FSP is setting a - * default policy that doesn't honor boards' requirements. */ - itss_snapshot_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); - /* Perform silicon specific init. */ fsp_silicon_init();
/* Display FIRMWARE_VERSION_INFO_HOB */ fsp_display_fvi_version_hob();
- /* Restore GPIO IRQ polarities back to previous settings. */ - itss_restore_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); - soc_fill_gpio_pm_configuration();
/* swap enabled PCI ports in device tree if needed */ diff --git a/src/soc/intel/tigerlake/chip.c b/src/soc/intel/tigerlake/chip.c index 4aa818e..024da15 100644 --- a/src/soc/intel/tigerlake/chip.c +++ b/src/soc/intel/tigerlake/chip.c @@ -127,19 +127,12 @@
void soc_init_pre_device(void *chip_info) { - /* Snapshot the current GPIO IRQ polarities. FSP is setting a - * default policy that doesn't honor boards' requirements. */ - itss_snapshot_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); - /* Perform silicon specific init. */ fsp_silicon_init();
/* Display FIRMWARE_VERSION_INFO_HOB */ fsp_display_fvi_version_hob();
- /* Restore GPIO IRQ polarities back to previous settings. */ - itss_restore_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); - soc_fill_gpio_pm_configuration();
/* Swap enabled PCI ports in device tree if needed. */
-
Aamir Bohra (Code Review)