Change in coreboot[master]: mb/prodrive/atlas: Configure PCIe device tree settings

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61296 )

Change subject: mb/prodrive/atlas: Configure PCIe device tree settings
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mb/prodrive/atlas: Configure PCIe device tree settings

Add CPU & PCH PCIe configs and remove the unused devices.
Configures per Atlas schematics v6.

Signed-off-by: Lean Sheng Tan 
Change-Id: Id3145156c4ab3ec1c2d3eb6c433108a1b1cab9e8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61296
Tested-by: build bot (Jenkins) 
Reviewed-by: Angel Pons 
Reviewed-by: Paul Menzel 
---
M src/mainboard/prodrive/atlas/devicetree.cb
1 file changed, 36 insertions(+), 9 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Paul Menzel: Looks good to me, but someone else must approve
  Angel Pons: Looks good to me, approved

diff --git a/src/mainboard/prodrive/atlas/devicetree.cb b/src/mainboard/prodrive/atlas/devicetree.cb
index ccda650..7b094e4 100644
--- a/src/mainboard/prodrive/atlas/devicetree.cb
+++ b/src/mainboard/prodrive/atlas/devicetree.cb
@@ -41,29 +41,56 @@
    	[PchSerialIoIndexUART2] = PchSerialIoDisabled,
    }"

+	# Enable PCH PCIE RP 5, 6, 7, 8, 9, 10 using free running CLK (0x80)
+	# Clock source is shared hence marked as free running.
+	register "pch_pcie_rp[PCH_RP(5)]" = "{
+		.flags = PCIE_RP_CLK_SRC_UNUSED,
+	}"
+	register "pch_pcie_rp[PCH_RP(6)]" = "{
+		.flags = PCIE_RP_CLK_SRC_UNUSED,
+	}"
+	register "pch_pcie_rp[PCH_RP(7)]" = "{
+		.flags = PCIE_RP_CLK_SRC_UNUSED,
+	}"
+	register "pch_pcie_rp[PCH_RP(8)]" = "{
+		.flags = PCIE_RP_CLK_SRC_UNUSED,
+	}"
+	register "pch_pcie_rp[PCH_RP(9)]" = "{
+		.flags = PCIE_RP_CLK_SRC_UNUSED,
+	}"
+	register "pch_pcie_rp[PCH_RP(10)]" = "{
+		.flags = PCIE_RP_CLK_SRC_UNUSED,
+	}"
+	register "pcie_clk_config_flag[0]" = "PCIE_CLK_FREE_RUNNING"
+	register "pcie_clk_config_flag[1]" = "PCIE_CLK_FREE_RUNNING"
+
+	# Enable CPU PCIE RP 1, 2, 3 using using free running CLK (0x80)
+	# Clock source is shared hence marked as free running.
+	register "cpu_pcie_rp[CPU_RP(1)]" = "{
+		.flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_SRC_UNUSED,
+	}"
+	register "cpu_pcie_rp[CPU_RP(2)]" = "{
+		.flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_SRC_UNUSED,
+	}"
+	register "cpu_pcie_rp[CPU_RP(3)]" = "{
+		.flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_SRC_UNUSED,
+	}"
+
    device domain 0 on
    	device ref pcie5 on end
    	device ref igpu on end
    	device ref dtt on end
    	device ref pcie4_0 on end
    	device ref pcie4_1 on end
-		device ref tbt_pcie_rp0 on end
-		device ref tbt_pcie_rp1 on end
-		device ref tbt_pcie_rp2 on end
-		device ref tbt_pcie_rp3 on end
    	device ref crashlog off end
    	device ref xhci on end
-		device ref cnvi_wifi on end
    	device ref heci1 on end
    	device ref sata on end
-		device ref pcie_rp1 on end
-		device ref pcie_rp3 on end # W/A to FSP issue
-		device ref pcie_rp4 on end # W/A to FSP issue
    	device ref pcie_rp5 on end
    	device ref pcie_rp6 on end
    	device ref pcie_rp8 on end
    	device ref pcie_rp9 on end
-		device ref pcie_rp11 on end
+		device ref pcie_rp10 on end
    	device ref uart0 on end
    	device ref uart1 on end
    	device ref p2sb on end

2 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.