[S] Change in coreboot[main]: cpu/x86/mtrr: Add soc_fill_uc_holes_in_physical_address_space

[Patrick Rudolph (Code Review)]

Attention is currently required from: Arthur Heymans, Christian Walter, Jincheng Li, Johnny Lin, Jonathan Zhang, Jérémy Compostella, Lean Sheng Tan, Nico Huber, Shuo Liu, Tim Chu.

Patrick Rudolph has posted comments on this change by Shuo Liu. ( https://review.coreboot.org/c/coreboot/+/82264?usp=email )

Change subject: cpu/x86/mtrr: Add soc_fill_uc_holes_in_physical_address_space
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Patch Set 8:

(1 comment)

File src/cpu/x86/mtrr/mtrr.c:

https://review.coreboot.org/c/coreboot/+/82264/comment/f38808f4_9ed60f32?usp... :
PS3, Line 203: soc_update_physical_address_space
> Raised https://review.coreboot.org/c/coreboot/+/82974, but still with opens. […]

Sorry, this snipped is hard to understand.

It sounds like the MTRR code should honour the MMIO window as reported by the domain:
```
[0m[SPEW ] DOMAIN: 00000000 resource base 200000000000 size 0 align 0 gran 0 limit 200fffffffff flags 40080200 index 3
```
but it does not since it doesn't have IORESOURCE_ASSIGNED set.