Attention is currently required from: Angel Pons, Felix Singer, Lean Sheng Tan, Maximilian Brune, Paul Menzel, Subrata Banik, Tim Wawrzynczak.
Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/66545?usp=email )
Change subject: mb/intel/adlrvp: Add ADL-S DDR5 UDIMM 1DPC ......................................................................
Patch Set 22:
(2 comments)
Patchset:
PS22:
I am not entirely sure what you mean. I only added an intel reference board. […]
Sorry, I was just trying to say is that this commit isn't adding the src/mainboard/intel/adlrvp directory, you're updating that mainboard directory by adding a variant. Since it's the intel subdirectory, it would be nice, though not required, to get an intel (or former intel) engineer to sign off on it - unless 9e is working for intel to add this.
There isn't anyone signed up as a maintainer for most of the intel boards though, so maybe it doesn't matter at all.
File src/mainboard/intel/adlrvp/devicetree_s.cb:
https://review.coreboot.org/c/coreboot/+/66545/comment/e8c85f85_ba677289 : PS22, Line 2: This really looks more like an override than a full mainboard devicetree. Looking at devicetree.cb, devicetree_m.cb, and devicetree_m.cb, those all have the full pci tree, including I2C chip configuration. Does this board just use the default PCI configuration from the chipset?
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Martin L Roth (Code Review)