Xiang Wang has uploaded this change for review. ( https://review.coreboot.org/28384
Change subject: riscv: add entry assembly file for RAMSTAGE ......................................................................
riscv: add entry assembly file for RAMSTAGE
RAMSTAGE will revoke CAR/scratchpad, so stack and exception handling needs to be moved to ddr memory. So add a assembly file to do this.
Change-Id: I58aa6ff911f385180bad6e026d3c3eace846e37d Signed-off-by: Xiang Wang wxjstz@126.com --- M src/arch/riscv/Makefile.inc A src/arch/riscv/assembly_entry.S M src/arch/riscv/include/arch/header.ld 3 files changed, 58 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/28384/1
diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc index c485940..4038964 100644 --- a/src/arch/riscv/Makefile.inc +++ b/src/arch/riscv/Makefile.inc @@ -97,6 +97,10 @@ ifeq ($(CONFIG_ARCH_RAMSTAGE_RISCV),y)
ramstage-y = +ramstage-y += assembly_entry.S +ramstage-y += mcall.c +ramstage-y += trap_util.S +ramstage-y += trap_handler.c ramstage-y += virtual_memory.c ramstage-y += stages.c ramstage-y += misc.c diff --git a/src/arch/riscv/assembly_entry.S b/src/arch/riscv/assembly_entry.S new file mode 100644 index 0000000..724de92 --- /dev/null +++ b/src/arch/riscv/assembly_entry.S @@ -0,0 +1,52 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/encoding.h> +#include <mcall.h> + +.section ".text._start", "ax", %progbits +.globl _start +_start: + # initialize stack point for each hart + # and the stack must be page-aligned. + # 0xDEADBEEF used to check stack overflow + csrr a0, mhartid + la t0, _stack + slli t1, a0, RISCV_PGSHIFT + add t0, t0, t1 + li t1, 0xDEADBEEF + sd t1, 0(t0) + li t1, RISCV_PGSIZE - HLS_SIZE + add sp, t0, t1 + + # initialize hart-local storage + csrr a0, mhartid + call hls_init + + # initialize entry of interrupt/exception + la t0, trap_entry + csrw mtvec, t0 + + # clear any pending interrupts + csrwi mip, 0 + + call exit_car + # set up the mstatus register for VM + call mstatus_init + tail main + + # These codes need to be implemented on a specific SoC + .weak exit_car +exit_car: + ret + diff --git a/src/arch/riscv/include/arch/header.ld b/src/arch/riscv/include/arch/header.ld index 3e078d8..2edcd67 100644 --- a/src/arch/riscv/include/arch/header.ld +++ b/src/arch/riscv/include/arch/header.ld @@ -23,6 +23,8 @@
#ifdef __BOOTBLOCK__ ENTRY(_start) +#elif __RAMSTAGE__ +ENTRY(_start) #else ENTRY(stage_entry) #endif
-
Xiang Wang (Code Review)