Patch set updated for coreboot: WIP: soc/intel/apollolake: Cache cbmem region

[Andrey Petrov]

Andrey Petrov ([e-mail]) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15456

-gerrit

commit d115cc2ed1ac97287125ffa7ec32ebde3efc3244
Author: Andrey Petrov 
Date:   Fri Jun 24 18:40:28 2016 -0700

WIP: soc/intel/apollolake: Cache cbmem region

Configure write-back MTRRs so that 8 MiB under cbmem_top is cached.
    This allows caching of FSP reserved memory and postcar stage itself.
    On CAR teardown the memory is flushed with clflush instruction.
    Depending on what cache configuration is used, either L1 (NEM) or
    both L1 and L2 (CQOS) storage is used for caching purposes.

This is WIP patch, because currently location of cbmem_top can not
    be known before memory is trained. So addresses are hardcoded.

BUG=chrome-os-partner:51959
    TEST=boot, notice cbmem showing MemoryInit getting ~140ms faster

Change-Id: I62aad238a3056f9bbe5327dfb33a2a1112d61194
    Signed-off-by: Andrey Petrov 
---
 src/soc/intel/apollolake/exit_car.S | 8 ++++++++
 src/soc/intel/apollolake/romstage.c | 8 ++++++++
 2 files changed, 16 insertions(+)

diff --git a/src/soc/intel/apollolake/exit_car.S b/src/soc/intel/apollolake/exit_car.S
index 86aadf5d..e5e8194 100644
--- a/src/soc/intel/apollolake/exit_car.S
+++ b/src/soc/intel/apollolake/exit_car.S
@@ -33,6 +33,14 @@ chipset_teardown_car:
    and	$(~(MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN)), %eax
    wrmsr

+	/* Flush all cache lines into the DRAM. */
+	mov	$0x7a800000, %eax
+loop:
+	clflush	(%eax)
+	add	$CACHE_LINE_SIZE, %eax
+	cmp	$0x7b000000, %eax
+	jl	loop
+
 #if IS_ENABLED(CONFIG_CAR_CQOS)
    mov	$MTRR_L2_QOS_MASK(0), %ecx
    rdmsr
diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c
index da7fcf1..b8aa52e 100644
--- a/src/soc/intel/apollolake/romstage.c
+++ b/src/soc/intel/apollolake/romstage.c
@@ -104,6 +104,7 @@ asmlinkage void car_stage_entry(void)
    struct postcar_frame pcf;
    uintptr_t top_of_ram;
    bool s3wake;
+	int mtrr;
    struct chipset_power_state *ps = car_get_var_ptr(&power_state);

timestamp_add_now(TS_START_ROMSTAGE);
@@ -115,6 +116,13 @@ asmlinkage void car_stage_entry(void)

s3wake = fill_power_state(ps) == ACPI_S3;

+	mtrr = get_free_var_mtrr();
+	if (mtrr==-1)
+		printk(BIOS_CRIT, "no available MTRRs to cache cbmem!\n");
+	else
+		/* Make sure cbmem 8 MiB under CBMEM is cachable */
+		set_var_mtrr(mtrr, 0x7a800000, 8*MiB, MTRR_TYPE_WRBACK);
+
    if (fsp_memory_init(s3wake) != FSP_SUCCESS) {
    	die("FSP memory init failed. Giving up.");
    }