Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37542 )
Change subject: ec/google/chromeec/acpi: move PS2K under PCI0 ......................................................................
ec/google/chromeec/acpi: move PS2K under PCI0
Commit 77ad581ce [chromeec: PS2K node can't be under SIO node] moved the PS2K ACPI device from under the SIO device to under the LPCB, and while this fixed the keyboard under Windows for Skylake devices, it was insufficient for Baytrail and Braswell devices (and likely Apollo Lake/Gemini Lake too).
Moving the PS2K device under PCI0 allows the PS2K to be functional under Windows for all Chrome-EC platforms.
Test: build/boot various Chrome-EC devices from IVB, HSW, BDW, BYT, SKL, BSW, and KBL platforms, verify keyboard functional under both Linux amd Windows 10.
Change-Id: If773eea69dc46030b6db9d64c3855be49951d4c0 Signed-off-by: Matt DeVillier matt.devillier@gmail.com --- M src/ec/google/chromeec/acpi/superio.asl 1 file changed, 30 insertions(+), 27 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/37542/1
diff --git a/src/ec/google/chromeec/acpi/superio.asl b/src/ec/google/chromeec/acpi/superio.asl index 9c0fa68..6f32a96 100644 --- a/src/ec/google/chromeec/acpi/superio.asl +++ b/src/ec/google/chromeec/acpi/superio.asl @@ -131,39 +131,42 @@ }
#ifdef SIO_EC_ENABLE_PS2K -Device (PS2K) // Keyboard +Scope (_SB.PCI0) { - Name (_UID, 0) - Name (_HID, "GOOG000A") - Name (_CID, Package() { EISAID("PNP0303"), EISAID("PNP030B") } ) - - Method (_STA, 0, NotSerialized) { - Return (0x0F) - } - - Name (_CRS, ResourceTemplate() + Device (PS2K) // Keyboard { - IO (Decode16, 0x60, 0x60, 0x01, 0x01) - IO (Decode16, 0x64, 0x64, 0x01, 0x01) -#ifdef SIO_EC_PS2K_IRQ - SIO_EC_PS2K_IRQ -#else - IRQ (Edge, ActiveHigh, Exclusive) {1} -#endif - }) + Name (_UID, 0) + Name (_HID, "GOOG000A") + Name (_CID, Package() { EISAID("PNP0303"), EISAID("PNP030B") } )
- Name (_PRS, ResourceTemplate() - { - StartDependentFn (0, 0) { + Method (_STA, 0, NotSerialized) { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate() + { IO (Decode16, 0x60, 0x60, 0x01, 0x01) IO (Decode16, 0x64, 0x64, 0x01, 0x01) -#ifdef SIO_EC_PS2K_IRQ + #ifdef SIO_EC_PS2K_IRQ SIO_EC_PS2K_IRQ -#else + #else IRQ (Edge, ActiveHigh, Exclusive) {1} -#endif - } - EndDependentFn () - }) + #endif + }) + + Name (_PRS, ResourceTemplate() + { + StartDependentFn (0, 0) { + IO (Decode16, 0x60, 0x60, 0x01, 0x01) + IO (Decode16, 0x64, 0x64, 0x01, 0x01) + #ifdef SIO_EC_PS2K_IRQ + SIO_EC_PS2K_IRQ + #else + IRQ (Edge, ActiveHigh, Exclusive) {1} + #endif + } + EndDependentFn () + }) + } } #endif
Hello Angel Pons, Stefan Reinauer, Furquan Shaikh, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/37542
to look at the new patch set (#2).
Change subject: ec/google/chromeec/acpi: move PS2K under PCI0 ......................................................................
ec/google/chromeec/acpi: move PS2K under PCI0
Commit 77ad581ce [chromeec: PS2K node can't be under SIO node] moved the PS2K ACPI device from under the SIO device to under the LPCB, and while this fixed the keyboard under Windows for Skylake devices, it was insufficient for Baytrail and Braswell devices (and likely Apollo Lake/Gemini Lake too).
Moving the PS2K device under PCI0 allows the PS2K to be functional under Windows for all Chrome-EC platforms.
Test: build/boot various Chrome-EC devices from IVB, HSW, BDW, BYT, SKL, BSW, and KBL platforms, verify keyboard functional under both Linux amd Windows 10.
Change-Id: If773eea69dc46030b6db9d64c3855be49951d4c0 Signed-off-by: Matt DeVillier matt.devillier@gmail.com --- M src/ec/google/chromeec/acpi/superio.asl 1 file changed, 27 insertions(+), 24 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/37542/2
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37542 )
Change subject: ec/google/chromeec/acpi: move PS2K under PCI0 ......................................................................
Patch Set 2:
(2 comments)
https://review.coreboot.org/c/coreboot/+/37542/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/37542/2//COMMIT_MSG@20 PS2, Line 20: amd and
https://review.coreboot.org/c/coreboot/+/37542/2//COMMIT_MSG@20 PS2, Line 20: Linux What version?
Hello Angel Pons, Stefan Reinauer, build bot (Jenkins), Patrick Georgi, Furquan Shaikh, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/37542
to look at the new patch set (#3).
Change subject: ec/google/chromeec/acpi: move PS2K under PCI0 ......................................................................
ec/google/chromeec/acpi: move PS2K under PCI0
Commit 77ad581ce [chromeec: PS2K node can't be under SIO node] moved the PS2K ACPI device from under the SIO device to under the LPCB, and while this fixed the keyboard under Windows for Skylake devices, it was insufficient for Baytrail and Braswell devices (and likely Apollo Lake/Gemini Lake too).
Moving the PS2K device under PCI0 allows the PS2K to be functional under Windows for all Chrome-EC platforms.
Test: build/boot various Chrome-EC devices from IVB, HSW, BDW, BYT, SKL, BSW, and KBL platforms, verify keyboard functional under both Linux (4.x and 5.x) and Windows 10.
Change-Id: If773eea69dc46030b6db9d64c3855be49951d4c0 Signed-off-by: Matt DeVillier matt.devillier@gmail.com --- M src/ec/google/chromeec/acpi/superio.asl 1 file changed, 27 insertions(+), 24 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/37542/3
Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37542 )
Change subject: ec/google/chromeec/acpi: move PS2K under PCI0 ......................................................................
Patch Set 3:
(2 comments)
https://review.coreboot.org/c/coreboot/+/37542/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/37542/2//COMMIT_MSG@20 PS2, Line 20: Linux
What version?
Done
https://review.coreboot.org/c/coreboot/+/37542/2//COMMIT_MSG@20 PS2, Line 20: amd
and
Done
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37542 )
Change subject: ec/google/chromeec/acpi: move PS2K under PCI0 ......................................................................
Patch Set 3: Code-Review+2
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37542 )
Change subject: ec/google/chromeec/acpi: move PS2K under PCI0 ......................................................................
Patch Set 3: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/37542 )
Change subject: ec/google/chromeec/acpi: move PS2K under PCI0 ......................................................................
ec/google/chromeec/acpi: move PS2K under PCI0
Commit 77ad581ce [chromeec: PS2K node can't be under SIO node] moved the PS2K ACPI device from under the SIO device to under the LPCB, and while this fixed the keyboard under Windows for Skylake devices, it was insufficient for Baytrail and Braswell devices (and likely Apollo Lake/Gemini Lake too).
Moving the PS2K device under PCI0 allows the PS2K to be functional under Windows for all Chrome-EC platforms.
Test: build/boot various Chrome-EC devices from IVB, HSW, BDW, BYT, SKL, BSW, and KBL platforms, verify keyboard functional under both Linux (4.x and 5.x) and Windows 10.
Change-Id: If773eea69dc46030b6db9d64c3855be49951d4c0 Signed-off-by: Matt DeVillier matt.devillier@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/37542 Reviewed-by: Angel Pons th3fanbus@gmail.com Reviewed-by: Furquan Shaikh furquan@google.com Reviewed-by: Paul Menzel paulepanter@users.sourceforge.net Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/ec/google/chromeec/acpi/superio.asl 1 file changed, 27 insertions(+), 24 deletions(-)
Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Furquan Shaikh: Looks good to me, approved Angel Pons: Looks good to me, approved
diff --git a/src/ec/google/chromeec/acpi/superio.asl b/src/ec/google/chromeec/acpi/superio.asl index 9c0fa68..fc5fc8c 100644 --- a/src/ec/google/chromeec/acpi/superio.asl +++ b/src/ec/google/chromeec/acpi/superio.asl @@ -131,30 +131,20 @@ }
#ifdef SIO_EC_ENABLE_PS2K -Device (PS2K) // Keyboard +Scope (_SB.PCI0) { - Name (_UID, 0) - Name (_HID, "GOOG000A") - Name (_CID, Package() { EISAID("PNP0303"), EISAID("PNP030B") } ) - - Method (_STA, 0, NotSerialized) { - Return (0x0F) - } - - Name (_CRS, ResourceTemplate() + Device (PS2K) // Keyboard { - IO (Decode16, 0x60, 0x60, 0x01, 0x01) - IO (Decode16, 0x64, 0x64, 0x01, 0x01) -#ifdef SIO_EC_PS2K_IRQ - SIO_EC_PS2K_IRQ -#else - IRQ (Edge, ActiveHigh, Exclusive) {1} -#endif - }) + Name (_UID, 0) + Name (_HID, "GOOG000A") + Name (_CID, Package() { EISAID("PNP0303"), EISAID("PNP030B") } )
- Name (_PRS, ResourceTemplate() - { - StartDependentFn (0, 0) { + Method (_STA, 0, NotSerialized) { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate() + { IO (Decode16, 0x60, 0x60, 0x01, 0x01) IO (Decode16, 0x64, 0x64, 0x01, 0x01) #ifdef SIO_EC_PS2K_IRQ @@ -162,8 +152,21 @@ #else IRQ (Edge, ActiveHigh, Exclusive) {1} #endif - } - EndDependentFn () - }) + }) + + Name (_PRS, ResourceTemplate() + { + StartDependentFn (0, 0) { + IO (Decode16, 0x60, 0x60, 0x01, 0x01) + IO (Decode16, 0x64, 0x64, 0x01, 0x01) +#ifdef SIO_EC_PS2K_IRQ + SIO_EC_PS2K_IRQ +#else + IRQ (Edge, ActiveHigh, Exclusive) {1} +#endif + } + EndDependentFn () + }) + } } #endif
-
Angel Pons (Code Review) -
Furquan Shaikh (Code Review)
-
Matt DeVillier (Code Review)
-
Patrick Georgi (Code Review)
-
Paul Menzel (Code Review)