[M] Change in coreboot[main]: mb/asus/p8z77-v: Attempt to correctly route PCIe lanes

[Keith Hui (Code Review)]

Attention is currently required from: Angel Pons, Bill XIE, Nicholas Chin.

Keith Hui has posted comments on this change by Keith Hui. ( https://review.coreboot.org/c/coreboot/+/85413?usp=email )

Change subject: mb/asus/p8z77-v: Attempt to correctly route PCIe lanes
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Patch Set 7:

(2 comments)

Patchset:

PS6:
> Looks like GPIO 5 is reset by either RSMRST# (pin 101) or SLPS5# (pin 84) depending on the setting i […]

According to the SIO datasheet I could temporarily change RSTOUT2# to GP76 using config register 0x2b and manually pulse the reset lines on the PCH PCIe slots this way. (I would need this one to be OD - it has a pull up.) Am I being too ambitious?

Looks like the root cause is a disruption of PCIe clock between PCIEX1_2 and ASM1061. Sadly the only reset signal ASM1061 gets is PLTRST#, so a system_reset() is still going to be necessary.

Patchset:

PS7: 
I implemented the additional logic Nicholas suggested. Let's give it a try.