Change in coreboot[master]: soc/intel/common/block/gpio: Port gpio code from Apollolake ...

[Hannah Williams (Code Review)]

Hannah Williams has posted comments on this change. ( https://review.coreboot.org/19759 )

Change subject: soc/intel/common/block/gpio: Port gpio code from Apollolake into common gpio
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Patch Set 9:

(5 comments)

https://review.coreboot.org/#/c/19759/8/src/soc/intel/common/block/include/i...
File src/soc/intel/common/block/include/intelblocks/gpio.h:

Line 35: };
> Presumably this has to increase if the number dwX registers increases per p

We should be able to extend this when needed and add the new ones inside a CONFIG flag which should get initialized using new macros

PS8, Line 38: 	gpio_t		first_pad;   /* first pad in community */
            : 	gpio_t		last_pad;    /* last pad in community */
            : 	uint8_t		port;
            : 	size_t		num_gpi_regs;/* number of gpi registers in community */
            : 	uint8_t		gpi_offset;  /* specifies offset in struct gpi_status */
            : 	const char	*name;
> Please rearrange these to make the size the smallest.

I missed to address this in patchset 9 - will fix

Line 56: const struct pad_community *gpio_get_community(gpio_t pad);
> Does this need to be exposed globally?

Yes this will be used from SOC dir

PS8, Line 87:  Returns the gpio group number
> From what? PMC route settings? If it's pmc it should be specified in the co

I missed to address this in patch set 9 - will fix

https://review.coreboot.org/#/c/19759/8/src/soc/intel/common/block/include/i...
File src/soc/intel/common/block/include/intelblocks/gpio_defs.h:

PS8, Line 65: #define  PAD_CFG0_RESET_RSMRST		(3 << 30)
> I'm not sure where this originally came from but it's right for APL.

This does have a conflict for SKL but it is not used in SKL code