Change in coreboot[master]: soc/intel/*:[WIP] enable FSP-M decompression at execution

[Rizwan Qureshi (Code Review)]

Rizwan Qureshi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63397 )

Change subject: soc/intel/*:[WIP] enable FSP-M decompression at execution
......................................................................

soc/intel/*:[WIP] enable FSP-M decompression at execution

FSP-M is compressed and is not more XIP. Hence remove the FSP_M_XIP config.
The FSP-M decompression requires more CAR memory. Increase CAR region size
to 2.5 MB. As per the system adress MAP we will be breaching the LAPIC base
address and HPET addresses hence rebase the CAR memory to somewhere safe.
Also increase the required stack szie

Signed-off-by: Rizwan Qureshi 
Change-Id: If2a20b0e81a116a81170363f7b93c845cde863f8
Signed-off-by: Rizwan Qureshi 
---
M src/soc/intel/alderlake/Kconfig
M src/soc/intel/common/block/cpu/car/cache_as_ram.S
2 files changed, 7 insertions(+), 7 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/63397/1

diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index 25d11d3..21b1767 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -134,17 +134,17 @@
    default 24

config DCACHE_RAM_BASE
-	default 0xfef00000
+	default 0xfa000000

config DCACHE_RAM_SIZE
-	default 0xc0000
+	default 0x280000
    help
      The size of the cache-as-ram region required during bootblock
      and/or romstage.

config DCACHE_BSP_STACK_SIZE
    hex
-	default 0x80400
+	default 0xC0000
    help
      The amount of anticipated stack usage in CAR by bootblock and
      other stages. In the case of FSP_USES_CB_STACK default value will be
diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S
index 1c905a4..c6f7f74 100644
--- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S
+++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S
@@ -178,7 +178,7 @@
    or	$MTRR_PHYS_MASK_VALID, %eax
    movl	%esi, %edx	/* edx <- MTRR_PHYS_MASK_HIGH */
    wrmsr
-#elif (CONFIG_DCACHE_RAM_SIZE == 768 * KiB) /* 768 KiB */
+#elif (CONFIG_DCACHE_RAM_SIZE == 2560 * KiB) /* 2560 KiB */
    find_free_mtrr
    test	%ebx, %ebx
    jz	.halt_forever
@@ -190,7 +190,7 @@
    wrmsr

incl	%ecx
-	mov	$(512 * KiB), %eax	/* size mask */
+	mov	$(2048 * KiB), %eax	/* size mask */
    dec	%eax
    not	%eax
    or	$MTRR_PHYS_MASK_VALID, %eax
@@ -201,13 +201,13 @@
    test	%ebx, %ebx
    jz	.halt_forever
 1:
-	mov	$(CONFIG_DCACHE_RAM_BASE + 512 * KiB), %eax
+	mov	$(CONFIG_DCACHE_RAM_BASE + 2048 * KiB), %eax
    or	$MTRR_TYPE_WRBACK, %eax
    xor	%edx,%edx
    wrmsr

incl	%ecx
-	mov	$(256 * KiB), %eax	/* size mask */
+	mov	$(512 * KiB), %eax	/* size mask */
    dec	%eax
    not	%eax
    or	$MTRR_PHYS_MASK_VALID, %eax