[L] Change in coreboot[main]: soc/intel/ptl: Define GPE1 macros and register fields

[Cliff Huang (Code Review)]

Attention is currently required from: Kapil Porwal, Paul Menzel, Pranava Y N.

Hello Kapil Porwal, Pranava Y N, Subrata Banik, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/84297?usp=email

to look at the new patch set (#10).

The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)

Change subject: soc/intel/ptl: Define GPE1 macros and register fields
......................................................................

soc/intel/ptl: Define GPE1 macros and register fields

New GPE1 bits are introduced in PTL for internal devices, incuding
PME_B0, hot plug, and PCIe events.
defines for GPE number for additional STD GPE0 in PTL
defines for GPE number for GPE1
defines for GPE1 bits
NOTE: All GEP1 bits are STD (Intel's Standard) GPE bits.

BUG=362310295
TEST=This cannot be tested directly.

Signed-off-by: Cliff Huang 
Change-Id: Iebf6f6d02b37cc9702e4ee07c1ec0017b6628836
---
M src/soc/intel/pantherlake/include/soc/gpe.h
M src/soc/intel/pantherlake/include/soc/pm.h
2 files changed, 369 insertions(+), 78 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/84297/10