Patch set updated for coreboot: fsp_model_406dx: use external microcode .h files for rangeley

[Martin Roth]

Martin Roth ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12335

-gerrit

commit b003aa6057ac10498430728a94a9ac5f003ddc54
Author: Martin Roth 
Date:   Thu Nov 5 09:00:20 2015 -0700

fsp_model_406dx: use external microcode .h files for rangeley

The microcode for the Rangeley chip is supplied as .h files in the
    Rangeley FSP POSTGOLD4 package.

When the rangeley microcode gets put into the blobs directory, this
    can be reverted and the binary file put into the makefile.

Change-Id: I30e7436f26a247bc9431f249becfa5fe8c581be7
    Signed-off-by: Martin Roth 
---
 src/cpu/intel/fsp_model_406dx/Kconfig      | 20 ++++++++------------
 src/cpu/intel/fsp_model_406dx/Makefile.inc |  3 ---
 2 files changed, 8 insertions(+), 15 deletions(-)

diff --git a/src/cpu/intel/fsp_model_406dx/Kconfig b/src/cpu/intel/fsp_model_406dx/Kconfig
index 30e7e59..2e58b35 100644
--- a/src/cpu/intel/fsp_model_406dx/Kconfig
+++ b/src/cpu/intel/fsp_model_406dx/Kconfig
@@ -28,11 +28,14 @@ config CPU_SPECIFIC_OPTIONS
    select SMP
    select SSE2
    select UDELAY_LAPIC
-	select SUPPORT_CPU_UCODE_IN_CBFS
+	select SUPPORT_CPU_UCODE_IN_CBFS if HAVE_FSP_BIN
    select PARALLEL_CPU_INIT
    select TSC_SYNC_MFENCE
    select LAPIC_MONOTONIC_TIMER

+	# Microcode header files are delivered in FSP package
+	select USES_MICROCODE_HEADER_FILES if HAVE_FSP_BIN
+
 choice
    prompt "Rangeley CPU Stepping"
    default FSP_MODEL_406DX_B0
@@ -58,16 +61,9 @@ config CPU_MICROCODE_CBFS_LOC
    depends on SUPPORT_CPU_UCODE_IN_CBFS
    default 0xfff60040

-config HAVE_CPU_MICROCODE_FILE
-	bool "Add microcode file"
-	help
-	  The microcode binary
-
-config CPU_MICROCODE_FILE
-	  string "Path and filename of CPU microcode"
-	  default "microcode.bin"
-	  depends on HAVE_CPU_MICROCODE_FILE
-	  help
-	    The path and filename of the file containing the CPU microcode.
+#set up microcode for rangeley POSTGOLD4 release
+config CPU_MICROCODE_HEADER_FILES
+	string
+	default "../intel/cpu/rangeley/microcode/microcode-m01406d000e.h ../intel/cpu/rangeley/microcode/microcode-m01406d8128.h"

endif #CPU_INTEL_FSP_MODEL_406DX
diff --git a/src/cpu/intel/fsp_model_406dx/Makefile.inc b/src/cpu/intel/fsp_model_406dx/Makefile.inc
index 91c7d96..3e29348 100644
--- a/src/cpu/intel/fsp_model_406dx/Makefile.inc
+++ b/src/cpu/intel/fsp_model_406dx/Makefile.inc
@@ -23,6 +23,3 @@ cpu_microcode_bins += $(call strip_quotes,$(CONFIG_CPU_MICROCODE_FILE))
 endif

CPPFLAGS_romstage += -I$(src)/cpu/intel/fsp_model_406dx
-# We don't have microcode for this CPU
-# Use CONFIG_CPU_MICROCODE_CBFS_EXTERNAL with a binary microcode file
-# cpu_microcode_bins += ???