Patch merged into coreboot/master: device/dram/ddr3: add FTB timings

the following patch was just integrated into master:
commit 76f8dbc4f70469e0b5913796d6130e85df1cdd77
Author: Nicola Corna 
Date:   Wed Nov 16 08:57:15 2016 +0100

device/dram/ddr3: add FTB timings

SPD revision 1.1 introduced FTB timings, an extra set of SPD values that
    specify a more precise tCKmin, tAAmin, tRCDmin, tRPmin and tRCmin.

For backwards compatibility, the MTB is usually rounded up and the FTB
    part is negative. For this reason some memories were not set up optimally,
    as the FTB part was ignored and the resulting timing wasn't set to the
    minimum value.

The tests were performed on a Lenovo X220 with two Micron 8KTF51264HZ-1G9E
    (1866 MHz): reading only the MTB part, coreboot reports a tCKmin of
    1.125 ns, corresponding to a working frequency of 800 MHz; with the
    additional tCKmin FTB part (-0.054 ns) the new (rounded) value is
    1.070 ns, valid for a 933 MHz operation.

Tested also with Ballistix DDR3-1866 SODIMM on Lenovo T420: the memory is
    now detected as DDR3-1866 instead of DDR3-1600.

Some manufacturers (like Micron) seems to expect a small rounding on the
    timings, so a nearest-value rounding is performed. If this assumption
    isn't correct, an error up to ~2 ps can be committed, which is low enough
    to be safely ignored.

Change-Id: Ib98f2e70820f207429d04ca6421680109a81f457
    Signed-off-by: Nicola Corna 
    Reviewed-on: https://review.coreboot.org/17476
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Rudolph 
    Reviewed-by: Paul Menzel

See https://review.coreboot.org/17476 for details.

-gerrit