Change in coreboot[master]: [WIP]mb/google/brya/var/kano: exchange i2c port for touchscreen/cr50

[David Wu (Code Review)]

Attention is currently required from: Tim Wawrzynczak.
David Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59473 )

Change subject: [WIP]mb/google/brya/var/kano: exchange i2c port for touchscreen/cr50
......................................................................

[WIP]mb/google/brya/var/kano: exchange i2c port for touchscreen/cr50

Exchange i2c port for touchscreen and cr50.

BUG=b:19583169
TEST=build pass

Signed-off-by: David Wu 
Change-Id: I5c900568adb119871d6374294a27195d75699ea6
---
M src/mainboard/google/brya/Kconfig
M src/mainboard/google/brya/variants/kano/gpio.c
M src/mainboard/google/brya/variants/kano/overridetree.cb
3 files changed, 130 insertions(+), 5 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/59473/1

diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index 136bde6..0fb904d 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -71,7 +71,15 @@

config DRIVER_TPM_I2C_BUS
    hex
-	default 0x3
+	default 0x3 if BOARD_GOOGLE_BRYA0
+	default 0x3 if BOARD_GOOGLE_BRASK
+	default 0x3 if BOARD_GOOGLE_PRIMUS
+	default 0x3 if BOARD_GOOGLE_GIMBLE
+	default 0x3 if BOARD_GOOGLE_REDRIX
+	default 0x1 if BOARD_GOOGLE_KANO
+	default 0x3 if BOARD_GOOGLE_TAEKO
+	default 0x3 if BOARD_GOOGLE_FELWINTER
+	default 0x3 if BOARD_GOOGLE_ANAHERA

config DRIVER_TPM_I2C_ADDR
    hex
diff --git a/src/mainboard/google/brya/variants/kano/gpio.c b/src/mainboard/google/brya/variants/kano/gpio.c
index 818ddd0..c7601e6 100644
--- a/src/mainboard/google/brya/variants/kano/gpio.c
+++ b/src/mainboard/google/brya/variants/kano/gpio.c
@@ -2,6 +2,7 @@

#include <baseboard/gpio.h>
 #include <baseboard/variants.h>
+#include <boardid.h>
 #include <commonlib/helpers.h>
 #include <soc/gpio.h>

@@ -161,6 +162,65 @@
    PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, DEEP, NF1),
 };

+/* Early pad configuration in bootblock for board id 1 */
+static const struct pad_config early_gpio_table_id1[] = {
+	/* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */
+	PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
+	/* B4  : PROC_GP3 ==> SSD_PERST_L */
+	PAD_CFG_GPO(GPP_B4, 0, DEEP),
+	/*
+	 * D1  : ISH_GP1 ==> FP_RST_ODL
+	 * FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down.
+	 * To ensure proper power sequencing for the FPMCU device, reset signal is driven low
+	 * early on in bootblock, followed by enabling of power. Reset signal is deasserted
+	 * later on in ramstage. Since reset signal is asserted in bootblock, it results in
+	 * FPMCU not working after a S3 resume. This is a known issue.
+	 */
+	PAD_CFG_GPO(GPP_D1, 0, DEEP),
+	/* D2  : ISH_GP2 ==> EN_FP_PWR */
+	PAD_CFG_GPO(GPP_D2, 1, DEEP),
+	/* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */
+	PAD_CFG_GPO(GPP_D11, 1, DEEP),
+	/* E0  : SATAXPCIE0 ==> NC */
+	PAD_NC(GPP_E0, NONE),
+	/* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */
+	PAD_CFG_GPI(GPP_E13, NONE, DEEP),
+	/* E15 : RSVD_TP ==> PCH_WP_OD */
+	PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP),
+	/* H6  : I2C1_SDA ==> PCH_I2C_TPM_SDA */
+	PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
+	/* H7  : I2C1_SCL ==> PCH_I2C_TPM_SCL */
+	PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
+	/* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
+	PAD_CFG_GPI(GPP_F18, NONE, DEEP),
+	/* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */
+	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
+	/* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */
+	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
+
+	/* CPU PCIe VGPIO for PEG60 */
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, DEEP, NF1),
+};
+
 static const struct pad_config romstage_gpio_table[] = {
    /* B4  : PROC_GP3 ==> SSD_PERST_L */
    PAD_CFG_GPO(GPP_B4, 1, DEEP),
@@ -174,8 +234,14 @@

const struct pad_config *variant_early_gpio_table(size_t *num)
 {
-	*num = ARRAY_SIZE(early_gpio_table);
-	return early_gpio_table;
+	const uint32_t id = board_id();
+	if (id == BOARD_ID_UNKNOWN || id < 1) {
+		*num = ARRAY_SIZE(early_gpio_table);
+		return early_gpio_table;
+	}
+
+	*num = ARRAY_SIZE(early_gpio_table_id1);
+	return early_gpio_table_id1;
 }

const struct pad_config *variant_romstage_gpio_table(size_t *num)
diff --git a/src/mainboard/google/brya/variants/kano/overridetree.cb b/src/mainboard/google/brya/variants/kano/overridetree.cb
index d7ae3da..4287f41 100644
--- a/src/mainboard/google/brya/variants/kano/overridetree.cb
+++ b/src/mainboard/google/brya/variants/kano/overridetree.cb
@@ -11,6 +11,10 @@
    	option UFC_USB			0
    	option UFC_MIPI_OVTI2740	1
    end
+	field TPM_I2C_BUS 38  38
+		option I2C_BUS_3		0
+		option I2C_BUS_1		1
+	end
 end
 chip soc/intel/alderlake
    register "SaGv" = "SaGv_Enabled"
@@ -246,7 +250,16 @@
    			register "key.linux_code" = "SW_PEN_INSERTED"
    			register "key.linux_input_type" = "EV_SW"
    			register "key.label" = ""pen_eject""
-				device generic 0 on end
+				device generic 0 on
+					probe TPM_I2C_BUS I2C_BUS_3
+				end
+			end
+			chip drivers/i2c/tpm
+				register "hid" = ""GOOG0005""
+				register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)"
+				device i2c 50 on
+					probe TPM_I2C_BUS I2C_BUS_1
+				end
    		end
    	end
    	device ref i2c2 on
@@ -408,7 +421,45 @@
    		chip drivers/i2c/tpm
    			register "hid" = ""GOOG0005""
    			register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)"
-				device i2c 50 on end
+				device i2c 50 on
+					probe TPM_I2C_BUS I2C_BUS_3
+				end
+			end
+			chip drivers/i2c/hid
+				register "generic.hid" = ""ELAN90FC""
+				register "generic.desc" = ""ELAN Touchscreen""
+				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)"
+				register "generic.probed" = "1"
+				register "generic.reset_gpio" =
+							"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
+				register "generic.reset_delay_ms" = "300"
+				register "generic.reset_off_delay_ms" = "1"
+				register "generic.enable_gpio" =
+							"ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
+				register "generic.enable_delay_ms" = "6"
+				register "generic.stop_gpio" =
+							"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)"
+				register "generic.stop_off_delay_ms" = "1"
+				register "generic.has_power_resource" = "1"
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 0x10 on
+					probe TPM_I2C_BUS I2C_BUS_1
+				end
+			end
+			chip drivers/generic/gpio_keys
+				register "name" = ""PENH""
+				# GPP_D6 is the IRQ source, and GPP_D17 is the wake source
+				register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPP_D6)"
+				register "key.wake_gpe" = "GPE0_DW1_17"
+				register "key.wakeup_route" = "WAKEUP_ROUTE_SCI"
+				register "key.wakeup_event_action" = "EV_ACT_DEASSERTED"
+				register "key.dev_name" = ""EJCT""
+				register "key.linux_code" = "SW_PEN_INSERTED"
+				register "key.linux_input_type" = "EV_SW"
+				register "key.label" = ""pen_eject""
+				device generic 0 on
+					probe TPM_I2C_BUS I2C_BUS_1
+				end
    		end
    	end
    	device ref i2c5 on