Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37816 )
Change subject: AGESA fam14: Remove early PCI subsystem ID setting ......................................................................
AGESA fam14: Remove early PCI subsystem ID setting
Change-Id: Id4e95c68517b01647049b5cbd50bf5a3974a9c3a Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/cpu/amd/agesa/family14/fixme.c 1 file changed, 0 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/37816/1
diff --git a/src/cpu/amd/agesa/family14/fixme.c b/src/cpu/amd/agesa/family14/fixme.c index 2b412fa..6fedd80 100644 --- a/src/cpu/amd/agesa/family14/fixme.c +++ b/src/cpu/amd/agesa/family14/fixme.c @@ -18,10 +18,6 @@ #include <AGESA.h> #include <amdlib.h>
-/* Define AMD Ontario APPU SSID/SVID */ -#define AMD_APU_SVID 0x1022 -#define AMD_APU_SSID 0x1234 - void amd_initcpuio(void) { UINT64 MsrReg; @@ -83,9 +79,6 @@ PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0, 0, 0xE0); PciData = 0x01308002; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0, 0, 0xE4); - PciData = (AMD_APU_SSID << 0x10) | AMD_APU_SVID; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
/* Set ROM cache onto WP to decrease post time */ MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | MTRR_TYPE_WRPROT;
Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37816 )
Change subject: AGESA fam14: Remove early PCI subsystem ID setting ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/37816/1/src/cpu/amd/agesa/family14/... File src/cpu/amd/agesa/family14/fixme.c:
https://review.coreboot.org/c/coreboot/+/37816/1/src/cpu/amd/agesa/family14/... PS1, Line 78: /* Set Ontario Link Data */ : PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0, 0, 0xE0); : PciData = 0x01308002; : LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); Remove these too. The subsystem ID is set via indexed registers.
Hello build bot (Jenkins), Michał Żygowski,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/37816
to look at the new patch set (#2).
Change subject: AGESA fam14: Remove early PCI subsystem ID setting ......................................................................
AGESA fam14: Remove early PCI subsystem ID setting
Change-Id: Id4e95c68517b01647049b5cbd50bf5a3974a9c3a Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/cpu/amd/agesa/family14/fixme.c 1 file changed, 0 insertions(+), 14 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/37816/2
Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37816 )
Change subject: AGESA fam14: Remove early PCI subsystem ID setting ......................................................................
Patch Set 3: Code-Review+2
Checked lspci -vvvxxxnnk before and after the change. No differences in any subsytem naming or driver used. I highly doubt it does anything.
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37816 )
Change subject: AGESA fam14: Remove early PCI subsystem ID setting ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/37816/1/src/cpu/amd/agesa/family14/... File src/cpu/amd/agesa/family14/fixme.c:
https://review.coreboot.org/c/coreboot/+/37816/1/src/cpu/amd/agesa/family14/... PS1, Line 78: /* Set Ontario Link Data */ : PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0, 0, 0xE0); : PciData = 0x01308002; : LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
Remove these too. The subsystem ID is set via indexed registers.
Done
Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/37816 )
Change subject: AGESA fam14: Remove early PCI subsystem ID setting ......................................................................
AGESA fam14: Remove early PCI subsystem ID setting
Change-Id: Id4e95c68517b01647049b5cbd50bf5a3974a9c3a Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/37816 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Michał Żygowski michal.zygowski@3mdeb.com --- M src/cpu/amd/agesa/family14/fixme.c 1 file changed, 0 insertions(+), 14 deletions(-)
Approvals: build bot (Jenkins): Verified Michał Żygowski: Looks good to me, approved
diff --git a/src/cpu/amd/agesa/family14/fixme.c b/src/cpu/amd/agesa/family14/fixme.c index 2b412fa..c9d3039 100644 --- a/src/cpu/amd/agesa/family14/fixme.c +++ b/src/cpu/amd/agesa/family14/fixme.c @@ -18,10 +18,6 @@ #include <AGESA.h> #include <amdlib.h>
-/* Define AMD Ontario APPU SSID/SVID */ -#define AMD_APU_SVID 0x1022 -#define AMD_APU_SSID 0x1234 - void amd_initcpuio(void) { UINT64 MsrReg; @@ -68,8 +64,6 @@ void amd_initmmio(void) { UINT64 MsrReg; - UINT32 PciData; - PCI_ADDR PciAddress; AMD_CONFIG_PARAMS StdHeader;
/* @@ -79,14 +73,6 @@ MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse(CONFIG_MMCONF_BUS_NUMBER) << 2) | 1; LibAmdMsrWrite(MMIO_CONF_BASE, &MsrReg, &StdHeader);
- /* Set Ontario Link Data */ - PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0, 0, 0xE0); - PciData = 0x01308002; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0, 0, 0xE4); - PciData = (AMD_APU_SSID << 0x10) | AMD_APU_SVID; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - /* Set ROM cache onto WP to decrease post time */ MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | MTRR_TYPE_WRPROT; LibAmdMsrWrite(MTRR_PHYS_BASE(6), &MsrReg, &StdHeader);
-
Kyösti Mälkki (Code Review) -
Michał Żygowski (Code Review)