Change in coreboot[master]: mb/intel/tglrvp: add Tiger Lake memory initialization support
Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38998 )
Change subject: mb/intel/tglrvp: add Tiger Lake memory initialization support ......................................................................
Patch Set 10:
(2 comments)
https://review.coreboot.org/c/coreboot/+/38998/9/src/mainboard/intel/tglrvp/... File src/mainboard/intel/tglrvp/romstage_fsp_params.c:
https://review.coreboot.org/c/coreboot/+/38998/9/src/mainboard/intel/tglrvp/... PS9, Line 84: mem_cfg->SpdAddressTable[0] = 0x0; What does this do?
https://review.coreboot.org/c/coreboot/+/38998/9/src/mainboard/intel/tglrvp/... File src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/variants.h:
https://review.coreboot.org/c/coreboot/+/38998/9/src/mainboard/intel/tglrvp/... PS9, Line 21: #include <soc/meminit_tgl.h> Please order alphabetically between lines 19 and 20.
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Nick Vaccaro (Code Review)