Change in coreboot[master]: WIP: mb/google/poppy/variants/nocturne: add dmic cofig params to DT

[Sathyanarayana Nujella (Code Review)]

Hello Jairaj Arava, HARSHAPRIYA N,

I'd like you to do a code review. Please visit

https://review.coreboot.org/28780

to review the following change.

Change subject: WIP: mb/google/poppy/variants/nocturne: add dmic cofig params to DT
......................................................................

WIP: mb/google/poppy/variants/nocturne: add dmic cofig params to DT

DMIC Codec needs minimum clock ON time to function it correctly
during switch from sleep-mode to wake-up mode.
Hence adding modeswitch_delay_ms as per DMIC spec.

BUG=b:112888584
TEST=Verified DT entry has modeswitch_delay_ms

Change-Id: Iabf1d2329880d7e247efac00d2160606792dab00
Signed-off-by: Sathyanarayana Nujella 
Signed-off-by: Jairaj Arava 
Signed-off-by: Harsha Priya 
---
M src/mainboard/google/poppy/variants/nocturne/devicetree.cb
1 file changed, 4 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/28780/1

diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
index 70a379c..6c3e007 100644
--- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
@@ -434,6 +434,10 @@
    		chip ec/google/chromeec
    			device pnp 0c09.0 on end
    		end
+			chip drivers/generic/dmic
+				register "modeswitch_delay_ms" = "35"
+				device generic 0 on end
+			end
    	end # LPC Interface
    	device pci 1f.1 on  end # P2SB
    	device pci 1f.2 on  end # Power Management Controller