Maximilian Brune has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80789?usp=email )
Change subject: Add Milk-V Pioneer mainboard and SOPHGO 2042 SOC ......................................................................
Add Milk-V Pioneer mainboard and SOPHGO 2042 SOC
Signed-off-by: Maximilian Brune maximilian.brune@9elements.com Change-Id: I6d953cc94733a364c7423992f08fdcb84762daf3 --- M src/arch/riscv/Kconfig M src/arch/riscv/tables.c M src/include/spi_sdcard.h A src/mainboard/milkv/Kconfig A src/mainboard/milkv/Kconfig.name A src/mainboard/milkv/pioneer/Kconfig A src/mainboard/milkv/pioneer/Kconfig.name A src/mainboard/milkv/pioneer/Makefile.inc A src/mainboard/milkv/pioneer/board_info.txt A src/mainboard/milkv/pioneer/devicetree.cb A src/mainboard/milkv/pioneer/mainboard.c A src/mainboard/milkv/pioneer/romstage.c A src/soc/sophgo/sg2042/Kconfig A src/soc/sophgo/sg2042/Makefile.inc A src/soc/sophgo/sg2042/cbmem.c A src/soc/sophgo/sg2042/chip.c A src/soc/sophgo/sg2042/clint.c A src/soc/sophgo/sg2042/clock.c A src/soc/sophgo/sg2042/gpio.c A src/soc/sophgo/sg2042/include/soc/addressmap.h A src/soc/sophgo/sg2042/include/soc/clock.h A src/soc/sophgo/sg2042/memlayout.ld A src/soc/sophgo/sg2042/spi.c A src/soc/sophgo/sg2042/uart.c 24 files changed, 602 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/80789/1
diff --git a/src/arch/riscv/Kconfig b/src/arch/riscv/Kconfig index 971dda3..d5ebfe6 100644 --- a/src/arch/riscv/Kconfig +++ b/src/arch/riscv/Kconfig @@ -109,5 +109,6 @@
config RISCV_WORKING_HARTID int + default 0
endif # if ARCH_RISCV diff --git a/src/arch/riscv/tables.c b/src/arch/riscv/tables.c index 9fc75f4..e94d83c 100644 --- a/src/arch/riscv/tables.c +++ b/src/arch/riscv/tables.c @@ -1,12 +1,53 @@ /* SPDX-License-Identifier: GPL-2.0-only */
+#include <acpi/acpi.h> +#include <assert.h> #include <bootmem.h> #include <boot/tables.h> #include <boot/coreboot_tables.h> +#include <cbmem.h> +#include <console/console.h> +#include <smbios.h> +#include <string.h> #include <symbols.h>
+//static void write_acpi_table(void) +// +// const size_t max_acpi_size = CONFIG_MAX_ACPI_TABLE_SIZE_KB * KiB; +// const uintptr_t acpi_start = (uintptr_t)cbmem_add(CBMEM_ID_ACPI, max_acpi_size); +// assert(IS_ALIGNED(acpi_start, 16)); +// const uintptr_t acpi_end = write_acpi_tables(acpi_start); +// assert(acpi_end < acpi_start + max_acpi_size); +// printk(BIOS_DEBUG, "ACPI tables: %ld bytes.\n", acpi_end - acpi_start); +//} +// +//static void write_smbios_table(void) +//{ +// unsigned long high_table_pointer, new_high_table_pointer; +//#define MAX_SMBIOS_SIZE (32 * KiB) +// high_table_pointer = (unsigned long)cbmem_add(CBMEM_ID_SMBIOS, MAX_SMBIOS_SIZE); +// if (!high_table_pointer) +// return; +// /* +// * Clear the entire region to ensure the unused space doesn't +// * contain garbage from a previous boot, like stale table +// * signatures that could be found by the OS. +// */ +// memset((void *)high_table_pointer, 0, MAX_SMBIOS_SIZE); +// new_high_table_pointer = smbios_write_tables(high_table_pointer); +// if (new_high_table_pointer > (high_table_pointer + MAX_SMBIOS_SIZE)) +// printk(BIOS_ERR, "Increase SMBIOS size\n"); +// printk(BIOS_DEBUG, "SMBIOS tables: %ld bytes.\n", +// new_high_table_pointer - high_table_pointer); +//} + void arch_write_tables(uintptr_t coreboot_table) { + //if (CONFIG(HAVE_ACPI_TABLES)) + // write_acpi_table(); + + //if (CONFIG(GENERATE_SMBIOS_TABLES)) + // write_smbios_table(); }
void bootmem_arch_add_ranges(void) diff --git a/src/include/spi_sdcard.h b/src/include/spi_sdcard.h index 8f64e5e..7dc1bd2 100644 --- a/src/include/spi_sdcard.h +++ b/src/include/spi_sdcard.h @@ -3,6 +3,7 @@ #ifndef _SPI_SDCARD_H_ #define _SPI_SDCARD_H_
+#include <spi-generic.h> #include <stddef.h>
struct spi_sdcard { diff --git a/src/mainboard/milkv/Kconfig b/src/mainboard/milkv/Kconfig new file mode 100644 index 0000000..1779954 --- /dev/null +++ b/src/mainboard/milkv/Kconfig @@ -0,0 +1,17 @@ +## SPDX-License-Identifier: GPL-2.0-only + +if VENDOR_MILKV + +choice + prompt "Mainboard model" + +source "src/mainboard/milkv/*/Kconfig.name" + +endchoice + +source "src/mainboard/milkv/*/Kconfig" + +config MAINBOARD_VENDOR + default "Milk-V" + +endif # VENDOR_MILKV diff --git a/src/mainboard/milkv/Kconfig.name b/src/mainboard/milkv/Kconfig.name new file mode 100644 index 0000000..845c7a7 --- /dev/null +++ b/src/mainboard/milkv/Kconfig.name @@ -0,0 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config VENDOR_MILKV + bool "Milk-V" diff --git a/src/mainboard/milkv/pioneer/Kconfig b/src/mainboard/milkv/pioneer/Kconfig new file mode 100644 index 0000000..8c8c9b1 --- /dev/null +++ b/src/mainboard/milkv/pioneer/Kconfig @@ -0,0 +1,23 @@ +if BOARD_MILKV_PIONEER + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select SOC_SOPHGO_SG2042 + select BOARD_ROMSIZE_KB_32768 + select MISSING_BOARD_RESET + #select FLATTENED_DEVICE_TREE + +config MAINBOARD_DIR + default "milkv/pioneer" + +config MAINBOARD_PART_NUMBER + default "" + +config MAINBOARD_SMBIOS_MANUFACTURER + string + default "SOPHGO" #TODO actually that is the SOC manufacturer + +config MAINBOARD_SMBIOS_PRODUCT_NAME + default "Sophgo SG2042 EVB Board" + +endif diff --git a/src/mainboard/milkv/pioneer/Kconfig.name b/src/mainboard/milkv/pioneer/Kconfig.name new file mode 100644 index 0000000..9dcbd5e --- /dev/null +++ b/src/mainboard/milkv/pioneer/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_MILKV_PIONEER + bool "Milk-V Pioneer" diff --git a/src/mainboard/milkv/pioneer/Makefile.inc b/src/mainboard/milkv/pioneer/Makefile.inc new file mode 100644 index 0000000..07e585c --- /dev/null +++ b/src/mainboard/milkv/pioneer/Makefile.inc @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0-only + +#CPPFLAGS_common += -Isrc/soc/sophgo/sg2042/include + +bootblock-y += romstage.c +bootblock-y += boot-media.c + +ramstage-y += boot-media.c diff --git a/src/mainboard/milkv/pioneer/board_info.txt b/src/mainboard/milkv/pioneer/board_info.txt new file mode 100644 index 0000000..c4ca892 --- /dev/null +++ b/src/mainboard/milkv/pioneer/board_info.txt @@ -0,0 +1,6 @@ +Category: eval +ROM package: SOIC-16 +ROM protocol: SPI +ROM socketed: n +Flashrom support: n +Board URL: https://www.crowdsupply.com/milk-v/milk-v-pioneer diff --git a/src/mainboard/milkv/pioneer/devicetree.cb b/src/mainboard/milkv/pioneer/devicetree.cb new file mode 100644 index 0000000..b28f60f --- /dev/null +++ b/src/mainboard/milkv/pioneer/devicetree.cb @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + +chip soc/sophgo/sg2042 + device cpu_cluster 0 on end +end diff --git a/src/mainboard/milkv/pioneer/mainboard.c b/src/mainboard/milkv/pioneer/mainboard.c new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/milkv/pioneer/mainboard.c diff --git a/src/mainboard/milkv/pioneer/romstage.c b/src/mainboard/milkv/pioneer/romstage.c new file mode 100644 index 0000000..b57c417 --- /dev/null +++ b/src/mainboard/milkv/pioneer/romstage.c @@ -0,0 +1,8 @@ +#include <romstage_common.h> + +void __noreturn romstage_main(void) +{ + //TODO + while (1) + ; +} diff --git a/src/soc/sophgo/sg2042/Kconfig b/src/soc/sophgo/sg2042/Kconfig new file mode 100644 index 0000000..c40c2d8 --- /dev/null +++ b/src/soc/sophgo/sg2042/Kconfig @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: GPL-2.0-only + +config SOC_SOPHGO_SG2042 + bool + select ARCH_RISCV_RV64 + select ARCH_RISCV_S + select ARCH_RISCV_U + select ARCH_RISCV_PMP + select ARCH_BOOTBLOCK_RISCV + select ARCH_VERSTAGE_RISCV + select ARCH_ROMSTAGE_RISCV + select ARCH_RAMSTAGE_RISCV + select DRIVERS_UART_8250MEM + select RISCV_USE_ARCH_TIMER + select UART_OVERRIDE_REFCLK + #select RISCV_HAS_OPENSBI + select NO_CBFS_MCACHE #TODO remove + select NO_FMAP_CACHE #TODO remove + +config SEPARATE_ROMSTAGE + bool + default n if SOC_SOPHGO_SG2042 + +if SOC_SOPHGO_SG2042 + +config COMPRESS_PRERAM_STAGES + bool + default n + +config MEMLAYOUT_LD_FILE + string + default "src/soc/sophgo/sg2042/memlayout.ld" + +config RISCV_ARCH + string + default "rv64imadc" + +config RISCV_ABI + string + default "lp64d" + +config RISCV_CODEMODEL + string + default "medany" + +config MAX_CPUS + int + default 64 + +config OPENSBI_PLATFORM + string + default "generic" + +config OPENSBI_TEXT_START + hex + default 0x80000000 + +endif diff --git a/src/soc/sophgo/sg2042/Makefile.inc b/src/soc/sophgo/sg2042/Makefile.inc new file mode 100644 index 0000000..45e5d23 --- /dev/null +++ b/src/soc/sophgo/sg2042/Makefile.inc @@ -0,0 +1,26 @@ +# SPDX-License-Identifier: GPL-2.0-only + +ifdef CONFIG_SOC_SOPHGO_SG2042 + +CPPFLAGS_common += -Isrc/soc/sophgo/sg2042/include + +bootblock-y += uart.c +bootblock-y += spi.c +bootblock-y += cbmem.c +#bootblock-y += clock.c +bootblock-y += chip.c +#bootblock-y += gpio.c +bootblock-y += clint.c +#bootblock-y += romstage.c + +ramstage-y += uart.c +ramstage-y += clint.c +ramstage-y += spi.c +ramstage-y += cbmem.c +ramstage-y += chip.c + +$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin + @printf " GPT $(notdir $(@))\n" + @util/riscv/sifive-gpt.py $< $@ + +endif # CONFIG_SOC_SOPHGO_SG2042 diff --git a/src/soc/sophgo/sg2042/cbmem.c b/src/soc/sophgo/sg2042/cbmem.c new file mode 100644 index 0000000..2fb5166 --- /dev/null +++ b/src/soc/sophgo/sg2042/cbmem.c @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <cbmem.h> +#include <commonlib/helpers.h> +#include <soc/addressmap.h> +#include <symbols.h> + +uintptr_t cbmem_top_chipset(void) +{ + return (uintptr_t)SG2042_DRAM + 32 * GiB; +} diff --git a/src/soc/sophgo/sg2042/chip.c b/src/soc/sophgo/sg2042/chip.c new file mode 100644 index 0000000..612a47d --- /dev/null +++ b/src/soc/sophgo/sg2042/chip.c @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <cbmem.h> +#include <device/device.h> +#include <symbols.h> + +static void sg2042_init(struct device *dev) +{ + int index = 0; + ram_from_to(dev, index++, (uintptr_t)_dram, (uintptr_t)cbmem_top()); +} + +struct chip_operations soc_sophgo_sg2042_ops = { + .name = ("Sopgho 2042"), + .enable_dev = sg2042_init, +}; + diff --git a/src/soc/sophgo/sg2042/clint.c b/src/soc/sophgo/sg2042/clint.c new file mode 100644 index 0000000..e78a314 --- /dev/null +++ b/src/soc/sophgo/sg2042/clint.c @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <mcall.h> +#include <stdint.h> +#include <device/mmio.h> +#include <soc/addressmap.h> + +void mtime_init(void) +{ + long hart_id = read_csr(mhartid); + HLS()->time = (uint64_t *)(SG2042_CLINT_TIMER + 0xbff8); + HLS()->timecmp = (uint64_t *)(SG2042_CLINT_TIMER + 0x4000 + 8 * hart_id); +} + +void set_msip(int hartid, int val) +{ + write32((void *)(SG2042_CLINT_IPI + 4 * (uintptr_t)hartid), !!val); +} diff --git a/src/soc/sophgo/sg2042/clock.c b/src/soc/sophgo/sg2042/clock.c new file mode 100644 index 0000000..754102f --- /dev/null +++ b/src/soc/sophgo/sg2042/clock.c @@ -0,0 +1,71 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +// This file is used for setting up clocks and get devices out of reset +// For more Information see FU740-C000 Manual Chapter 7 Clocking and Reset + +#include <console/console.h> +#include <delay.h> +#include <device/mmio.h> +#include <soc/addressmap.h> +#include <soc/clock.h> +//#include <soc/gpio.h> +#include <gpio.h> +#include <stdint.h> + +// according to TRM this is the reference clock for all the PLLs: +// - PLL_CLK_IN_MAIN +// - PLL_CLK_IN_DDR_L +// - PLL_CLK_IN_DDR_R +#define SG2042_FREQ (25 * MHz) + +// Mode select: +// MODE_SEL2 MODE_SEL1 MODE_SEL0 MODE +// x 0 0 Normal +// x 0 1 Fast +// x 1 0 Safe +// x 1 1 Bypass + + +// Clock NORMAL(MHz) FAST(MHz) SAFE(MHz) BYPASS(MHz) +// ========================================================= +// MPLL 1600 2000 1000 25 +// FPLL 1000 1000 1000 25 +// DPLL0 1200 1600 800 25 +// DPLL1 1200 1600 800 25 +// RISC-V CPU 1600 2000 1000 25 +// RISC-V Timer 50 50 50 25 +// SLC 800 1000 500 25 +// SYSDMA 250 250 250 25 +// UART SCLK 500 500 250 25 +// UART PCLK 250 250 250 25 +// DBG_I2C 250 250 250 25 +// LPC 200 200 200 25 +// BOOTROM 100 100 100 25 +// SPI Flash 100 100 100 25 +// BOOTRAM 100 100 100 25 +// TIMER PCLK 100 100 100 25 +// TIMER1 50 50 50 25 +// TIMER2 50 50 50 25 +// TIMER3 50 50 50 25 +// TIMER4 50 50 50 25 +// TIMER5 50 50 50 25 +// TIMER6 50 50 50 25 +// TIMER7 50 50 50 25 +// TIMER8 50 50 50 25 +// EFUSE CLK 25 25 25 25 +// EFUSE PCLK 100 100 100 25 +// GPIO PCLK 100 100 100 25 +// GPIO INTR CLK 100 100 100 25 +// GPIO DBCLK 0.1 0.1 0.1 0.1 +// SPI SSI 250 250 250 25 +// SPI PCLK 250 250 250 25 +// IIC ICCLK 100 100 100 25 +// IIC PCLK 100 100 100 25 +// WDT 100 100 100 25 +// PWM 100 100 100 25 +// RTC 100 100 100 25 +// PCIE0/1/2/3 800 1000 500 25 +// HSDMA 800 1000 500 25 +// DDR0/1/2/3 1200 1600 800 25 + + diff --git a/src/soc/sophgo/sg2042/gpio.c b/src/soc/sophgo/sg2042/gpio.c new file mode 100644 index 0000000..9e87cf8 --- /dev/null +++ b/src/soc/sophgo/sg2042/gpio.c @@ -0,0 +1,86 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <soc/addressmap.h> +#include <soc/gpio.h> +#include <stdint.h> +#include <arch/mmio.h> +#include <delay.h> +#include <assert.h> +#include <device/mmio.h> +#include <gpio.h> + +#define SIFIVE_GPIO_INPUT_VAL (FU740_GPIO + 0x00) +#define SIFIVE_GPIO_INPUT_EN (FU740_GPIO + 0x04) +#define SIFIVE_GPIO_OUTPUT_EN (FU740_GPIO + 0x08) +#define SIFIVE_GPIO_OUTPUT_VAL (FU740_GPIO + 0x0C) +#define SIFIVE_GPIO_PUE (FU740_GPIO + 0x10) +#define SIFIVE_GPIO_DS (FU740_GPIO + 0x14) +#define SIFIVE_GPIO_RISE_IE (FU740_GPIO + 0x18) +#define SIFIVE_GPIO_RISE_IP (FU740_GPIO + 0x1C) +#define SIFIVE_GPIO_FALL_IE (FU740_GPIO + 0x20) +#define SIFIVE_GPIO_FALL_IP (FU740_GPIO + 0x24) +#define SIFIVE_GPIO_HIGH_IE (FU740_GPIO + 0x28) +#define SIFIVE_GPIO_HIGH_IP (FU740_GPIO + 0x2C) +#define SIFIVE_GPIO_LOW_IE (FU740_GPIO + 0x30) +#define SIFIVE_GPIO_LOW_IP (FU740_GPIO + 0x34) +#define SIFIVE_GPIO_IOF_EN (FU740_GPIO + 0x38) +#define SIFIVE_GPIO_IOF_SEL (FU740_GPIO + 0x3C) +#define SIFIVE_GPIO_OUT_XOR (FU740_GPIO + 0x40) + +// for debugging purposes +static void gpio_dump(void) +{ + printk(BIOS_DEBUG, "input_val : %x\n", read32((void *)SIFIVE_GPIO_INPUT_VAL)); + printk(BIOS_DEBUG, "input_en : %x\n", read32((void *)SIFIVE_GPIO_INPUT_EN)); + printk(BIOS_DEBUG, "output_en : %x\n", read32((void *)SIFIVE_GPIO_OUTPUT_EN)); + printk(BIOS_DEBUG, "output_val: %x\n", read32((void *)SIFIVE_GPIO_OUTPUT_VAL)); + printk(BIOS_DEBUG, "pue : %x\n", read32((void *)SIFIVE_GPIO_PUE)); + printk(BIOS_DEBUG, "ds : %x\n", read32((void *)SIFIVE_GPIO_DS)); + printk(BIOS_DEBUG, "rise_ie : %x\n", read32((void *)SIFIVE_GPIO_RISE_IE)); + printk(BIOS_DEBUG, "rise_ip : %x\n", read32((void *)SIFIVE_GPIO_RISE_IP)); + printk(BIOS_DEBUG, "fall_ie : %x\n", read32((void *)SIFIVE_GPIO_FALL_IE)); + printk(BIOS_DEBUG, "fall_ip : %x\n", read32((void *)SIFIVE_GPIO_FALL_IP)); + printk(BIOS_DEBUG, "high_ie : %x\n", read32((void *)SIFIVE_GPIO_HIGH_IE)); + printk(BIOS_DEBUG, "high_ip : %x\n", read32((void *)SIFIVE_GPIO_HIGH_IP)); + printk(BIOS_DEBUG, "low_ie : %x\n", read32((void *)SIFIVE_GPIO_LOW_IE)); + printk(BIOS_DEBUG, "low_ip : %x\n", read32((void *)SIFIVE_GPIO_LOW_IP)); + printk(BIOS_DEBUG, "iof_en : %x\n", read32((void *)SIFIVE_GPIO_IOF_EN)); + printk(BIOS_DEBUG, "iof_sel : %x\n", read32((void *)SIFIVE_GPIO_IOF_SEL)); + printk(BIOS_DEBUG, "out_xor : %x\n", read32((void *)SIFIVE_GPIO_OUT_XOR)); +} + +void gpio_set(gpio_t gpio, int value) +{ + uint32_t output_val = read32((void *)SIFIVE_GPIO_OUTPUT_VAL); + + if (value) + output_val |= (1 << gpio); + else + output_val &= ~(1 << gpio); + + write32((void *)SIFIVE_GPIO_OUTPUT_VAL, output_val); +} + +int gpio_get(gpio_t gpio) +{ + uint32_t input_val = read32((void *)SIFIVE_GPIO_INPUT_VAL); + return !!(input_val & (1 << gpio)); +} + +void gpio_set_direction(gpio_t gpio, enum gpio_direction gpio_dir) +{ + uint32_t input_en = read32((void *)SIFIVE_GPIO_INPUT_EN); + uint32_t output_en = read32((void *)SIFIVE_GPIO_OUTPUT_EN); + + if (gpio_dir == GPIO_OUTPUT) { + input_en &= ~(1 << gpio); + output_en |= (1 << gpio); + } else if (gpio_dir == GPIO_INPUT) { + input_en |= (1 << gpio); + output_en &= ~(1 << gpio); + } + + write32((void *)SIFIVE_GPIO_INPUT_EN, input_en); + write32((void *)SIFIVE_GPIO_OUTPUT_EN, output_en); +} diff --git a/src/soc/sophgo/sg2042/include/soc/addressmap.h b/src/soc/sophgo/sg2042/include/soc/addressmap.h new file mode 100644 index 0000000..daf22da --- /dev/null +++ b/src/soc/sophgo/sg2042/include/soc/addressmap.h @@ -0,0 +1,90 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_SG2042_ADDRESSMAP_H_ +#define _SOC_SG2042_ADDRESSMAP_H_ + +#define SG2042_DRAM +#define SG2042_CLINT + +// C23 digit separator I NEED YOU +// Start Address - End Address Devices Memory Size +// 0x00000000000 - 0x00FFFFFFFFF DDR0 64G +// 0x01000000000 - 0x01FFFFFFFFF DDR1 64G +// 0x02000000000 - 0x02FFFFFFFFF DDR2 64G +// 0x03000000000 - 0x03FFFFFFFFF DDR3 64G +// 0x04000000000 - 0x043FFFFFFFF PCIE0_LINK0_SLAVE 16G +// 0x04400000000 - 0x047FFFFFFFF PCIE0_LINK1_SLAVE 16G +// 0x04800000000 - 0x04BFFFFFFFF PCIE1_LINK0_SLAVE 16G +// 0x04C00000000 - 0x04FFFFFFFFF PCIE1_LINK1_SLAVE 16G +// 0x07000140000 - 0x0700014FFFF SCP_ROM 64K +// 0x07000180000 - 0x0700117FFFF Serial_Flash0 16M +// 0x07002180000 - 0x0700317FFFF Serial_Flash1 16M +// 0x07008000000 - 0x0700FFFFFFF LPC 128M +// 0x07010000000 - 0x070100FFFFF SRAM0 1M +// 0x07010100000 - 0x070101FFFFF SRAM1 1M +// 0x07030000000 - 0x07030000FFF EFUSE0 4K +// 0x07030001000 - 0x07030001FFF EFUSE1 4K +// 0x07030002000 - 0x07030002FFF RTC 4K +// 0x07030003000 - 0x07030003FFF TIMER 4K +// 0x07030004000 - 0x07030004FFF WDT 4K +// 0x07030005000 - 0x07030005FFF I2C0 4K +// 0x07030006000 - 0x07030006FFF I2C1 4K +// 0x07030007000 - 0x07030007FFF I2C2 4K +// 0x07030008000 - 0x07030008FFF I2C3 4K +// 0x07030009000 - 0x07030009FFF GPIO0 4K +// 0x0703000A000 - 0x0703000AFFF GPIO1 4K +// 0x0703000B000 - 0x0703000BFFF GPIO2 4K +// 0x0703000C000 - 0x0703000CFFF PWM 4K +// 0x07030010000 - 0x07030017FFF SYS_CTRL 32K (from 2023) +// 0x07030010000 - 0x07030017FFF SYS_CTRL 4K (from 2024) +// 0x07030011000 - 0x07030011FFF PINMUX 4K (from 2024) +// 0x07030012000 - 0x07030012FFF CLOCK 4K (from 2024) +// 0x07030013000 - 0x07030013FFF RESET 4K (from 2024) +// 0x07040000000 - 0x07040000FFF UART0 4K +// 0x07040001000 - 0x07040001FFF UART1 4K +// 0x07040002000 - 0x07040002FFF UART2 4K +// 0x07040003000 - 0x07040003FFF UART3 4K +// 0x07040004000 - 0x07040004FFF SPI0 4K +// 0x07040005000 - 0x07040005FFF SPI1 4K +// 0x07040006000 - 0x07040015FFF SYS_DMA 64K +// 0x07040016000 - 0x07040025FFF HS_DMA 64K +// 0x07040026000 - 0x07040029FFF ETH0 16K +// 0x0704002A000 - 0x0704002AFFF EMMC0 4K +// 0x0704002B000 - 0x0704002BFFF EMMC1 4K +// 0x070400A0000 - 0x0704029FFFF TOP_Monitor 2M +// 0x070402A0000 - 0x0704049FFFF HSPERI_Monitor 2M +// 0x07050000000 - 0x07051FFFFFF DDR0_CFG 32M +// 0x07052000000 - 0x07053FFFFFF DDR1_CFG 32M +// 0x07054000000 - 0x07055FFFFFF DDR2_CFG 32M +// 0x07056000000 - 0x07057FFFFFF DDR3_CFG 32M +// 0x07060000000 - 0x07061FFFFFF PCIE0_CFG 32M +// 0x07062000000 - 0x07063FFFFFF PCIE1_CFG 32M +// 0x07070000000 - 0x0707FFFFFFF MESH 256M +// 0x07090000000 - 0x07093FFFFFF PLIC 64M +// 0x07094000000 - 0x07097FFFFFF CLINT_IPI 64M +// 0x070AC000000 - 0x070AFFFFFFF CLINT_TIMER 64M + +#define SG2042_DRAM0 0x00000000000 + +#define SG2042_SCP_ROM 0x07000140000 + +#define SG2042_SERIAL_FLASH0 0x07000180000 +#define SG2042_SERIAL_FLASH1 0x07002180000 + +#define SG2042_SRAM0 0x07010000000 +#define SG2042_SRAM1 0x07010100000 + +#define SG2042_UART(x) (SG2042_UART0 + x * 0x1000) +#define SG2042_UART0 0x07040000000 +#define SG2042_UART1 0x07040001000 +#define SG2042_UART2 0x07040002000 +#define SG2042_UART3 0x07040003000 + +#define SG2042_SPI0 0x07040004000 +#define SG2042_SPI1 0x07040005000 + +#define SG2042_CLINT_IPI 0x07094000000 +#define SG2042_CLINT_TIMER 0x070AC000000 + + +#endif // _SOC_SG2042_ADDRESSMAP_H_ diff --git a/src/soc/sophgo/sg2042/include/soc/clock.h b/src/soc/sophgo/sg2042/include/soc/clock.h new file mode 100644 index 0000000..d4ed400 --- /dev/null +++ b/src/soc/sophgo/sg2042/include/soc/clock.h @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_SG2042_CLOCK_H_ +#define _SOC_SG2042_CLOCK_H_ + +// these are the offsets relative to the CLOCK memory map region +#define CLKENREG0 0x0000 +#define CLKENREG1 0x0004 +#define CLKSELREG0 0x0020 + +#define CLKDIVREG0 0x0040 +#define CLKDIVREG1 0x0044 +#define CLKDIVREG2 0x0048 +#define CLKDIVREG3 0x004c +#define CLKDIVREG4 0x0050 +#define CLKDIVREG5 0x0054 +#define CLKDIVREG6 0x0058 +#define CLKDIVREG7 0x005c +#define CLKDIVREG8 0x0060 +#define CLKDIVREG9 0x0064 +#define CLKDIVREG10 0x0068 +#define CLKDIVREG11 0x006c +#define CLKDIVREG12 0x0070 +#define CLKDIVREG13 0x0074 +#define CLKDIVREG14 0x0078 +#define CLKDIVREG15 0x007c +#define CLKDIVREG16 0x0080 +#define CLKDIVREG17 0x0084 +#define CLKDIVREG18 0x0088 +#define CLKDIVREG19 0x008c +#define CLKDIVREG20 0x0090 +#define CLKDIVREG21 0x0094 +#define CLKDIVREG22 0x0098 +#define CLKDIVREG23 0x009c +#define CLKDIVREG24 0x00a0 +#define CLKDIVREG25 0x00a4 +#define CLKDIVREG26 0x00a8 +#define CLKDIVREG27 0x00ac +#define CLKDIVREG28 0x00b0 +#define CLKDIVREG29 0x00b4 +#define CLKDIVREG30 0x00b8 + +#endif // _SOC_SG2042_CLOCK_H_ diff --git a/src/soc/sophgo/sg2042/memlayout.ld b/src/soc/sophgo/sg2042/memlayout.ld new file mode 100644 index 0000000..3fe68e6 --- /dev/null +++ b/src/soc/sophgo/sg2042/memlayout.ld @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <memlayout.h> +#include <soc/addressmap.h> + +#include <arch/header.ld> + +#CONFIG_RAM_START=0x40000000 +#CONFIG_RAM_SIZE=0x200000 +#CONFIG_ARCH_SET_TIMER_FREQ=y +#CONFIG_ARCH_TIMER_FREQ=10000000 + +SECTIONS +{ + // maybe: 0x80000000 + DRAM_START(0x40000000) + /* The 64K size is not allocated. It's just for basic size checking. */ + BOOTBLOCK(., 64K) + . = ALIGN(4K); + CAR_STACK(., 12K) // considering each harts stack is a pagesize (4K), we can potentially have up to 16 harts regarding stack space //TODO reduce it, since fu740 doesn't even have/support 16 harts + PRERAM_CBMEM_CONSOLE(., 8K) + CBFS_MCACHE(., 8K) + FMAP_CACHE(., 2K) + PRERAM_CBFS_CACHE(., 128K) + + //OPENSBI(., 256K) + /* The 256K size is not allocated. It's just for basic size checking. */ + //TODO check why ramstage needs to be 2M ... + RAMSTAGE(., 2M) + . = ALIGN(4K); + MEM_STACK(., 20K) + POSTRAM_CBFS_CACHE(., 32M - 256K - 256K - 20K) + + //DRAM_END(SG2042_DDR0 + 64G) +} diff --git a/src/soc/sophgo/sg2042/spi.c b/src/soc/sophgo/sg2042/spi.c new file mode 100644 index 0000000..5a62e21 --- /dev/null +++ b/src/soc/sophgo/sg2042/spi.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +//TODO needs work + +#include <device/mmio.h> +#include <soc/addressmap.h> +#include <delay.h> +#include <lib.h> + diff --git a/src/soc/sophgo/sg2042/uart.c b/src/soc/sophgo/sg2042/uart.c new file mode 100644 index 0000000..80d0348 --- /dev/null +++ b/src/soc/sophgo/sg2042/uart.c @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <stdint.h> +#include <console/uart.h> +#include <commonlib/bsd/helpers.h> +#include <soc/addressmap.h> +#include <soc/clock.h> + +uintptr_t uart_platform_base(unsigned int idx) +{ + if (idx < 4) + return SG2042_UART(idx); + else + return 0; +} + +unsigned int uart_platform_refclk(void) +{ + // peripheral clock is attached to UART subsystem + //return clock_get_pclk(); + return 500 * MHz; +}
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Maximilian Brune (Code Review)