Change in coreboot[master]: mb/intel/adlrvp: Enable HECI1 communication

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52149 )

Change subject: mb/intel/adlrvp: Enable HECI1 communication
......................................................................

mb/intel/adlrvp: Enable HECI1 communication

The patch enables HECI1 interface to allow OS applications to communicate
with CSE.

BUG=None
TEST=Build and boot ADLRVP. Run lspci and check pcie device (00:16.0)

Signed-off-by: Sridhar Siricilla 
Change-Id: I34ff842481bdfc7933a76555ff0fd70f4fbbb9a7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52149
Tested-by: build bot (Jenkins) 
Reviewed-by: Rizwan Qureshi 
Reviewed-by: Maulik V Vaghela 
---
M src/mainboard/intel/adlrvp/devicetree.cb
1 file changed, 3 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Rizwan Qureshi: Looks good to me, approved
  Maulik V Vaghela: Looks good to me, approved

diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb
index cade987..57d78de 100644
--- a/src/mainboard/intel/adlrvp/devicetree.cb
+++ b/src/mainboard/intel/adlrvp/devicetree.cb
@@ -12,6 +12,9 @@
    register "pmc_gpe0_dw1" = "GPP_D"
    register "pmc_gpe0_dw2" = "GPP_E"

+	# Enable HECI1 interface
+	register "HeciEnabled" = "1"
+
    # FSP configuration

# Enable CNVi BT