Mario Scheithauer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33196
Change subject: siemens/mc_apl5: Change PTN interface settings ......................................................................
siemens/mc_apl5: Change PTN interface settings
Switch the clock output for single LVDS mode to odd bus only.
Change-Id: I278e761566a112d95cbd6c79e09c076d70b93e8f Signed-off-by: Mario Scheithauer mario.scheithauer@siemens.com --- M src/mainboard/siemens/mc_apl1/variants/mc_apl5/ptn3460.c 1 file changed, 2 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/33196/1
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/ptn3460.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/ptn3460.c index c0770f3..c655218 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/ptn3460.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/ptn3460.c @@ -76,7 +76,8 @@ return (PTN_BUS_ERROR | status); /* Set up configuration data according to the hwinfo block we get. */ cfg.dp_interface_ctrl = 0; - cfg.lvds_interface_ctrl1 = 0x00; + /* Use odd-bus for clock distribution only. */ + cfg.lvds_interface_ctrl1 = 0x01; if (disp_con == PF_DISPLCON_LVDS_DUAL) /* Turn on dual LVDS lane and clock. */ cfg.lvds_interface_ctrl1 |= 0x0b;
Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33196 )
Change subject: siemens/mc_apl5: Change PTN interface settings ......................................................................
Patch Set 1: Code-Review+1
(1 comment)
https://review.coreboot.org/#/c/33196/1/src/mainboard/siemens/mc_apl1/varian... File src/mainboard/siemens/mc_apl1/variants/mc_apl5/ptn3460.c:
https://review.coreboot.org/#/c/33196/1/src/mainboard/siemens/mc_apl1/varian... PS1, Line 79: - No need for the hyphen here. What you want to do here is to drive the clock on the odd bus per default. If there is a need for dual lane, hwinfo data will enable the even bus in addition. So maybe change this comment to: Drive LVDS clock on odd bus per default.
But it is up to you.
Hello Werner Zeh, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/33196
to look at the new patch set (#2).
Change subject: siemens/mc_apl5: Change PTN interface settings ......................................................................
siemens/mc_apl5: Change PTN interface settings
Switch the default clock output for single LVDS mode to odd bus only.
Change-Id: I278e761566a112d95cbd6c79e09c076d70b93e8f Signed-off-by: Mario Scheithauer mario.scheithauer@siemens.com --- M src/mainboard/siemens/mc_apl1/variants/mc_apl5/ptn3460.c 1 file changed, 2 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/33196/2
Mario Scheithauer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33196 )
Change subject: siemens/mc_apl5: Change PTN interface settings ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/#/c/33196/1/src/mainboard/siemens/mc_apl1/varian... File src/mainboard/siemens/mc_apl1/variants/mc_apl5/ptn3460.c:
https://review.coreboot.org/#/c/33196/1/src/mainboard/siemens/mc_apl1/varian... PS1, Line 79: -
No need for the hyphen here. […]
You are right, that's the default setting.
Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33196 )
Change subject: siemens/mc_apl5: Change PTN interface settings ......................................................................
Patch Set 2: Code-Review+2
Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/33196 )
Change subject: siemens/mc_apl5: Change PTN interface settings ......................................................................
siemens/mc_apl5: Change PTN interface settings
Switch the default clock output for single LVDS mode to odd bus only.
Change-Id: I278e761566a112d95cbd6c79e09c076d70b93e8f Signed-off-by: Mario Scheithauer mario.scheithauer@siemens.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/33196 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Werner Zeh werner.zeh@siemens.com --- M src/mainboard/siemens/mc_apl1/variants/mc_apl5/ptn3460.c 1 file changed, 2 insertions(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Werner Zeh: Looks good to me, approved
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/ptn3460.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/ptn3460.c index c0770f3..f6fed97 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/ptn3460.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/ptn3460.c @@ -76,7 +76,8 @@ return (PTN_BUS_ERROR | status); /* Set up configuration data according to the hwinfo block we get. */ cfg.dp_interface_ctrl = 0; - cfg.lvds_interface_ctrl1 = 0x00; + /* Drive LVDS clock for single mode on odd bus per default. */ + cfg.lvds_interface_ctrl1 = 0x01; if (disp_con == PF_DISPLCON_LVDS_DUAL) /* Turn on dual LVDS lane and clock. */ cfg.lvds_interface_ctrl1 |= 0x0b;
-
Mario Scheithauer (Code Review) -
Patrick Georgi (Code Review)
-
Werner Zeh (Code Review)