[S] Change in coreboot[main]: nb/intel/sandybridge: assign PCIe root port ops in chipset devicetree

[Felix Held (Code Review)]

Attention is currently required from: Angel Pons.

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79115?usp=email )

Change subject: nb/intel/sandybridge: assign PCIe root port ops in chipset devicetree
......................................................................

nb/intel/sandybridge: assign PCIe root port ops in chipset devicetree

Since the PCIe root ports in the northbridge are always on the same
device functions, the device operations can be statically assigned in
the devicetree and there's no need to bind the host bridge device
operations to the PCI device during runtime via a list of PCI IDs.

Signed-off-by: Felix Held 
Change-Id: I357aa0b27fcc73814f60d0aa5b5141add8917825
---
M src/northbridge/intel/sandybridge/chipset.cb
M src/northbridge/intel/sandybridge/pcie.c
2 files changed, 5 insertions(+), 17 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/79115/1

diff --git a/src/northbridge/intel/sandybridge/chipset.cb b/src/northbridge/intel/sandybridge/chipset.cb
index 38a53d5..61e86e4 100644
--- a/src/northbridge/intel/sandybridge/chipset.cb
+++ b/src/northbridge/intel/sandybridge/chipset.cb
@@ -11,12 +11,12 @@
    device domain 0 on
    	ops sandybridge_pci_domain_ops
    	device pci 00.0 alias host_bridge on ops sandybridge_host_bridge_ops end
-		device pci 01.0 alias peg10 off end # PEG10
-		device pci 01.1 alias peg11 off end # PEG11
-		device pci 01.2 alias peg12 off end # PEG12
+		device pci 01.0 alias peg10 off ops sandybridge_nb_pcie_rp_ops end # PEG10
+		device pci 01.1 alias peg11 off ops sandybridge_nb_pcie_rp_ops end # PEG11
+		device pci 01.2 alias peg12 off ops sandybridge_nb_pcie_rp_ops end # PEG12
    	device pci 02.0 alias igd off ops sandybridge_gma_func0_ops end # vga controller
    	device pci 04.0 alias dev4 off end # Device 4
-		device pci 06.0 alias peg60 off end # PEG60
+		device pci 06.0 alias peg60 off ops sandybridge_nb_pcie_rp_ops end # PEG60

chip southbridge/intel/bd82x6x # Intel Series 6/7 PCH
    		device pci 14.0 alias xhci off end       # USB 3.0 Controller (only on 7 series)
diff --git a/src/northbridge/intel/sandybridge/pcie.c b/src/northbridge/intel/sandybridge/pcie.c
index ec737a2..deb50b9 100644
--- a/src/northbridge/intel/sandybridge/pcie.c
+++ b/src/northbridge/intel/sandybridge/pcie.c
@@ -43,7 +43,7 @@
 }
 #endif

-static struct device_operations device_ops = {
+struct device_operations sandybridge_nb_pcie_rp_ops = {
    .read_resources		= pci_bus_read_resources,
    .set_resources		= pci_dev_set_resources,
    .enable_resources	= pci_bus_enable_resources,
@@ -55,15 +55,3 @@
    .acpi_name		= pcie_acpi_name,
 #endif
 };
-
-static const unsigned short pci_device_ids[] = {
-	0x0101, 0x0105, 0x0109, 0x010d,
-	0x0151, 0x0155, 0x0159, 0x015d,
-	0,
-};
-
-static const struct pci_driver pch_pcie __pci_driver = {
-	.ops		= &device_ops,
-	.vendor		= PCI_VID_INTEL,
-	.devices	= pci_device_ids,
-};