[M] Change in coreboot[main]: mb/google/brya/var/nivviks: Support for discrete/integrated wifi module
Poornima Tom has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82172?usp=email )
Change subject: mb/google/brya/var/nivviks: Support for discrete/integrated wifi module ......................................................................
mb/google/brya/var/nivviks: Support for discrete/integrated wifi module
Enabled both discrete & integrated wifi module using fw config. This is intended to support both wifi6 & wifi7 modules. Integrated cnvi based wifi module has wifi6 & discrete pcie based wifi module supports wifi7.
BUG=NONE BRANCH=NONE TEST=Verified Wifi6/7 module detection
After making fw config changes in cbi settings with bit 7 set, discrete wifi module(wifi7) is getting detected. On switching back to default fw config settings(bit 7 cleared), integrated wifi6 module is geting detected.
Change-Id: Ibea9688714a53440e5ac3a57505ed7c8f9cd4250 Signed-off-by: Poornima Tom poornima.tom@intel.com --- M src/mainboard/google/brya/variants/nivviks/gpio.c M src/mainboard/google/brya/variants/nivviks/overridetree.cb 2 files changed, 185 insertions(+), 11 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/82172/1
diff --git a/src/mainboard/google/brya/variants/nivviks/gpio.c b/src/mainboard/google/brya/variants/nivviks/gpio.c index c61ac2a..fd33efc 100644 --- a/src/mainboard/google/brya/variants/nivviks/gpio.c +++ b/src/mainboard/google/brya/variants/nivviks/gpio.c @@ -5,6 +5,7 @@ #include <boardid.h> #include <commonlib/helpers.h> #include <soc/gpio.h> +#include <fw_config.h>
/* Pad configuration in ramstage for nivviks board_id = 0 */ static const struct pad_config board_id0_overrides[] = { @@ -44,6 +45,40 @@ PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2), };
+/* Pad configuration for board with pcie wifi */ +static const struct pad_config board_id0_has_pcie_wifi_gpio_overrides[] = { + /* A8 : WWAN_RF_DISABLE_ODL */ + PAD_CFG_GPO(GPP_A8, 1, DEEP), + /* D6 : WWAN_EN */ + PAD_CFG_GPO(GPP_D6, 1, DEEP), + /* F12 : WWAN_RST_L */ + PAD_CFG_GPO_LOCK(GPP_F12, 1, LOCK_CONFIG), + /* H19 : SOC_I2C_SUB_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_H19, NONE, PLTRST, LEVEL, NONE), + /* H23 : WWAN_SAR_DETECT_ODL */ + PAD_CFG_GPO(GPP_H23, 1, DEEP), + /* R4 : I2S2_SCLK ==> I2S_SPK_BCLK_R */ + PAD_CFG_NF(GPP_R4, NONE, DEEP, NF2), + /* R5 : I2S2_SFRM ==> I2S_SPK_LRCK_R */ + PAD_CFG_NF(GPP_R5, NONE, DEEP, NF2), + /* R6 : I2S2_TXD ==> I2S_SPK_AUDIO_R */ + PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2), + /* R7 : I2S2_RXD ==> NC */ + PAD_NC(GPP_R7, NONE), + /* S0 : NC */ + PAD_NC(GPP_S0, NONE), + /* S1 : NC */ + PAD_NC(GPP_S1, NONE), + /* S2 : DMIC_CKL_A_0 ==> DMIC_UCAM_CLK_R */ + PAD_CFG_NF(GPP_S2, NONE, DEEP, NF2), + /* S3 : DMIC_DATA_0 ==> DMIC_UCAM_DATA */ + PAD_CFG_NF(GPP_S3, NONE, DEEP, NF2), + /* S6 : DMIC_CLK_A_1 ==> DMIC_WCAM_CLK_R */ + PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2), + /* S7 : DMIC_DATA_1 ==> DMIC_WCAM_DATA */ + PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2), +}; + /* Pad configuration in ramstage for nivviks board_id >= 1 */ static const struct pad_config override_gpio_table[] = { /* A8 : WWAN_RF_DISABLE_ODL */ @@ -80,6 +115,41 @@ PAD_CFG_NF(GPP_VGPIO_37, NONE, DEEP, NF1), };
+/* + * Pad configuration in ramstage for nivviks board_id >= 1 with pcie + * wifi + */ +static const struct pad_config board_has_pcie_wifi_override_gpio_table[] = { + /* A8 : WWAN_RF_DISABLE_ODL */ + PAD_CFG_GPO(GPP_A8, 1, DEEP), + /* D6 : WWAN_EN */ + PAD_CFG_GPO(GPP_D6, 1, DEEP), + /* F12 : WWAN_RST_L */ + PAD_CFG_GPO_LOCK(GPP_F12, 1, LOCK_CONFIG), + /* H19 : SOC_I2C_SUB_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_H19, NONE, PLTRST, LEVEL, NONE), + /* H23 : WWAN_SAR_DETECT_ODL */ + PAD_CFG_GPO(GPP_H23, 1, DEEP), + + /* Configure the virtual CNVi Bluetooth I2S GPIO pads */ + /* BT_I2S_BCLK */ + PAD_CFG_NF(GPP_VGPIO_30, NONE, DEEP, NF3), + /* BT_I2S_SYNC */ + PAD_CFG_NF(GPP_VGPIO_31, NONE, DEEP, NF3), + /* BT_I2S_SDO */ + PAD_CFG_NF(GPP_VGPIO_32, NONE, DEEP, NF3), + /* BT_I2S_SDI */ + PAD_CFG_NF(GPP_VGPIO_33, NONE, DEEP, NF3), + /* SSP2_SCLK */ + PAD_CFG_NF(GPP_VGPIO_34, NONE, DEEP, NF1), + /* SSP2_SFRM */ + PAD_CFG_NF(GPP_VGPIO_35, NONE, DEEP, NF1), + /* SSP_TXD */ + PAD_CFG_NF(GPP_VGPIO_36, NONE, DEEP, NF1), + /* SSP_RXD */ + PAD_CFG_NF(GPP_VGPIO_37, NONE, DEEP, NF1), +}; + /* Pad configuration in ramstage for nirwen */ static const struct pad_config override_gpio_table_nirwen[] = { /* A8 : WWAN_RF_DISABLE_ODL */ @@ -150,6 +220,34 @@ PAD_CFG_GPO(GPP_H13, 1, DEEP), };
+/* Early pad configuration in bootblock for nivviks with pcie wifi */ +static const struct pad_config early_gpio_table_for_board_with_pcie_wifi[] = { + /* F12 : GSXDOUT ==> WWAN_RST_L */ + PAD_CFG_GPO(GPP_F12, 0, DEEP), + /* H12 : UART0_RTS# ==> SD_PERST_L */ + PAD_CFG_GPO(GPP_H12, 0, DEEP), + /* H20 : IMGCLKOUT1 ==> WLAN_PERST_L */ + PAD_CFG_GPO(GPP_H20, 0, DEEP), + /* A13 : GPP_A13 ==> GSC_SOC_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), + /* D6 : SRCCLKREQ1# ==> WWAN_EN */ + PAD_CFG_GPO(GPP_D6, 1, DEEP), + /* E12 : THC0_SPI1_IO1 ==> SOC_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_E12, NONE, DEEP), + /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_F18, NONE, DEEP), + /* H4 : I2C0_SDA ==> SOC_I2C_GSC_SDA */ + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), + /* H5 : I2C0_SCL ==> SOC_I2C_GSC_SCL */ + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), + /* H10 : UART0_RXD ==> UART_SOC_RX_DBG_TX */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), + /* H11 : UART0_TXD ==> UART_SOC_TX_DBG_RX */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), + /* H13 : UART0_CTS# ==> EN_PP3300_SD_X */ + PAD_CFG_GPO(GPP_H13, 1, DEEP), +}; + /* Early pad configuration in bootblock for nirwen */ static const struct pad_config early_gpio_table_nirwen[] = { /* B4 : SSD_PERST_L */ @@ -194,17 +292,45 @@ PAD_CFG_GPO(GPP_H12, 1, DEEP), };
+static const struct pad_config board_wifi_pcie_romstage_gpio_table[] = { + /* B4 : SSD_PERST_L */ + PAD_CFG_GPO(GPP_B4, 1, DEEP), + + /* Enable touchscreen, hold in reset */ + /* C0 : SMBCLK ==> EN_PP3300_TCHSCR */ + PAD_CFG_GPO(GPP_C0, 1, DEEP), + /* C1 : SMBDATA ==> USI_RST_L */ + PAD_CFG_GPO(GPP_C1, 0, DEEP), + + /* H12 : UART0_RTS# ==> SD_PERST_L */ + PAD_CFG_GPO(GPP_H12, 1, DEEP), + /* H20 : IMGCLKOUT1 ==> WLAN_PERST_L */ + PAD_CFG_GPO(GPP_H20, 1, DEEP), +}; + const struct pad_config *variant_gpio_override_table(size_t *num) { const uint32_t id = board_id(); - if (id == BOARD_ID_UNKNOWN || id == 0) { - *num = ARRAY_SIZE(board_id0_overrides); - return board_id0_overrides; + if (id == BOARD_ID_UNKNOWN || id == 0) { + if (fw_config_probe(FW_CONFIG(WIFI_TYPE, WIFI_PCIE))) { + *num = ARRAY_SIZE(board_id0_has_pcie_wifi_gpio_overrides); + return board_id0_has_pcie_wifi_gpio_overrides; + } + else { + *num = ARRAY_SIZE(board_id0_overrides); + return board_id0_overrides; + } }
if (id == 1) { - *num = ARRAY_SIZE(override_gpio_table); - return override_gpio_table; + if (fw_config_probe(FW_CONFIG(WIFI_TYPE, WIFI_PCIE))) { + *num = ARRAY_SIZE(board_has_pcie_wifi_override_gpio_table); + return board_has_pcie_wifi_override_gpio_table; + } + else { + *num = ARRAY_SIZE(override_gpio_table); + return override_gpio_table; + } }
/* board_id >= 2 means nirwen */ @@ -216,8 +342,14 @@ { const uint32_t id = board_id(); if (id == BOARD_ID_UNKNOWN || id < 2) { - *num = ARRAY_SIZE(early_gpio_table); - return early_gpio_table; + if (fw_config_probe(FW_CONFIG(WIFI_TYPE, WIFI_PCIE))) { + *num = ARRAY_SIZE(early_gpio_table_for_board_with_pcie_wifi); + return early_gpio_table_for_board_with_pcie_wifi; + } + else { + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; + } }
/* board_id >= 2 means nirwen */ @@ -228,6 +360,12 @@
const struct pad_config *variant_romstage_gpio_table(size_t *num) { - *num = ARRAY_SIZE(romstage_gpio_table); - return romstage_gpio_table; + if (fw_config_probe(FW_CONFIG(WIFI_TYPE, WIFI_PCIE))) { + *num = ARRAY_SIZE(board_wifi_pcie_romstage_gpio_table); + return board_wifi_pcie_romstage_gpio_table; + } + else { + *num = ARRAY_SIZE(romstage_gpio_table); + return romstage_gpio_table; + } } diff --git a/src/mainboard/google/brya/variants/nivviks/overridetree.cb b/src/mainboard/google/brya/variants/nivviks/overridetree.cb index d7be804..b2988b1 100644 --- a/src/mainboard/google/brya/variants/nivviks/overridetree.cb +++ b/src/mainboard/google/brya/variants/nivviks/overridetree.cb @@ -20,6 +20,10 @@ option STYLUS_PRESENT 0 option STYLUS_ABSENT 1 end + field WIFI_TYPE 7 + option WIFI_CNVI 0 + option WIFI_PCIE 1 + end end
chip soc/intel/alderlake @@ -38,6 +42,7 @@ register "typec_aux_bias_pads[1]" = "{.pad_auxp_dc = GPP_A21, .pad_auxn_dc = GPP_A22}"
register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for CNVi WLAN + register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for WIFI PCIE
# Configure external V1P05/Vnn/VnnSx Rails register "ext_fivr_settings" = "{ @@ -285,7 +290,9 @@ device ref cnvi_wifi on chip drivers/wifi/generic register "enable_cnvi_ddr_rfim" = "true" - device generic 0 on end + device generic 0 on + probe WIFI_TYPE WIFI_CNVI + end end end device ref i2c1 on @@ -496,6 +503,30 @@ device generic 0 on end end end + device ref pcie_rp4 on + probe WIFI_TYPE WIFI_PCIE + # Enable WLAN Card PCIE 4 using clk 2 + register "pch_pcie_rp[PCH_RP(4)]" = "{ + .clk_src = 2, + .clk_req = 2, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + chip drivers/wifi/generic + register "wake" = "GPE0_DW1_03" + register "add_acpi_dma_property" = "true" + device pci 00.0 on + probe WIFI_TYPE WIFI_PCIE + end + end + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B11)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H20)" + register "srcclk_pin" = "2" + device generic 0 on + probe WIFI_TYPE WIFI_PCIE + end + end + end #PCIE4 WLAN card device ref pcie_rp7 on # Enable SD Card PCIe 7 using clk 3 register "pch_pcie_rp[PCH_RP(7)]" = "{ @@ -626,7 +657,12 @@ register "type" = "UPC_TYPE_INTERNAL" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)" - device ref usb2_port10 on end + device ref usb2_port10 on + probe WIFI_TYPE WIFI_CNVI + end + device ref usb2_port8 on + probe WIFI_TYPE WIFI_PCIE + end end chip drivers/usb/acpi register "desc" = ""USB3 Type-A Port A0 (MLB)""
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Poornima Tom (Code Review)