Change in coreboot[master]: soc/intel/common/block/tco: clear TCO1_STS register, too

[Michael Niewöhner (Code Review)]

Hello Shaunak Saha, build bot (Jenkins), Nico Huber, Patrick Georgi, Lee Leahy, Subrata Banik, Kyösti Mälkki, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/39259

to look at the new patch set (#2).

Change subject: soc/intel/common/block/tco: clear TCO1_STS register, too
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soc/intel/common/block/tco: clear TCO1_STS register, too

The register TCO1_STS is never cleared, which will cause SMIs to either
retrigger over and over again (e.g. TIMEOUT) or prevent concurrent
interrupt events, depending on which event triggered.

Clear both TCO2_STS and TCO1_STS.

This also fixes the issue where SECOND_TO_STS will always end up set in
the SMI handler by unconditionally (re)setting it.

Tested on X11SSM-F, where enabling TCO caused the terminal to get
flooded with SMI debug messages. With this patch, a message gets written
every ~1 second.

Signed-off-by: Michael Niewöhner 
Change-Id: Ia57c203a672fdd0095355a7e2a0e01aaa6657968
---
M src/soc/intel/common/block/smbus/tco.c
1 file changed, 5 insertions(+), 5 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/39259/2