Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/29662
Change subject: soc/intel/braswell: Add C_ENVIRONMENT_BOOTBLOCK support ......................................................................
soc/intel/braswell: Add C_ENVIRONMENT_BOOTBLOCK support
No working C_ENVIRONMENT_BOOTBLOCK support is available. Enable support and add required files for the Braswell Bootblock in C.
BUG=NA TEST=Portwell PQ7-M107
Change-Id: Iab48ad72f1514c93f20d70db5ef4fd8fa2383e8c Signed-off-by: Frans Hendriks fhendriks@eltan.com --- M src/drivers/intel/fsp1_1/Makefile.inc A src/drivers/intel/fsp1_1/cache_as_ram_cbootblock.S M src/soc/intel/braswell/Kconfig M src/soc/intel/braswell/Makefile.inc A src/soc/intel/braswell/bootblock/bootblock_c.c A src/soc/intel/braswell/include/soc/bootblock.h M src/soc/intel/braswell/romstage/Makefile.inc A src/soc/intel/braswell/romstage/car_stage.S 8 files changed, 329 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/29662/1
diff --git a/src/drivers/intel/fsp1_1/Makefile.inc b/src/drivers/intel/fsp1_1/Makefile.inc index 953d1e4..3b3387e 100644 --- a/src/drivers/intel/fsp1_1/Makefile.inc +++ b/src/drivers/intel/fsp1_1/Makefile.inc @@ -3,6 +3,7 @@ # # Copyright (C) 2014 Sage Electronic Engineering, LLC. # Copyright (C) 2015 Intel Corp. +# Copyright (C) 2018 Eltan B.V. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -22,6 +23,7 @@
bootblock-y += bootblock.c bootblock-y += fsp_util.c +bootblock-$(CONFIG_C_ENVIRONMENT_BOOTBLOCK)+= cache_as_ram_cbootblock.S
romstage-y += car.c romstage-y += fsp_util.c diff --git a/src/drivers/intel/fsp1_1/cache_as_ram_cbootblock.S b/src/drivers/intel/fsp1_1/cache_as_ram_cbootblock.S new file mode 100644 index 0000000..70f36a4 --- /dev/null +++ b/src/drivers/intel/fsp1_1/cache_as_ram_cbootblock.S @@ -0,0 +1,215 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000,2007 Ronald G. Minnich rminnich@gmail.com + * Copyright (C) 2007-2008 coresystems GmbH + * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. + * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2018 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/pci_def.h> +#include <cpu/x86/mtrr.h> +#include <cpu/x86/cache.h> +#include <cpu/x86/cr.h> +#include <cpu/x86/post_code.h> +#include <../../../../../arch/x86/walkcbfs.S> + +#define LHLT_DELAY 0x50000 /* I/O delay between post codes */ + +.global bootblock_pre_c_entry +bootblock_pre_c_entry: + +.global cache_as_ram +cache_as_ram: + post_code(0x20) + +#if IS_ENABLED(CONFIG_SKIP_FSP_CAR) + /* + * SOC specific setup + * NOTE: This has to preserve the registers + * mm0, mm1 and edi. + */ + #include <soc/car_setup.S> + + post_code(0x28) +#endif + + /* + * Find the FSP binary in cbfs. + * Make a fake stack that has the return value back to this code. + */ + lea fake_fsp_stack, %esp + jmp find_fsp +find_fsp_ret: + /* Save the FSP location */ + mov %eax, %ebp + + /* + * Only when a valid FSP binary is found at CONFIG_FSP_LOC is + * the returned FSP_INFO_HEADER structure address above the base + * address of FSP binary specified by the CONFIG_FSP_LOC value. + * All of the error values are in the 0x8xxxxxxx range which are + * below the CONFIG_FSP_LOC value. + */ + cmp $CONFIG_FSP_LOC, %eax + jbe halt1 + + post_code(POST_FSP_TEMP_RAM_INIT) + + /* Calculate entry into FSP */ + mov 0x30(%ebp), %eax /* Load TempRamInitEntry */ + add 0x1c(%ebp), %eax /* add in the offset for FSP */ + + /* + * Pass early init variables on a fake stack (no memory yet) + * as well as the return location + */ + lea CAR_init_stack, %esp + + /* + * BIST value is zero + * eax: TempRamInitApi address + * ebp: FSP_INFO_HEADER address + * edi: BIST value + * esi: Not used + * mm0: low 32-bits of TSC value + * mm1: high 32-bits of TSC value + */ + + /* call FSP binary to setup temporary stack */ + jmp *%eax + +CAR_init_done: + addl $4, %esp + + /* + * ebp: FSP_INFO_HEADER address + * ecx: Temp RAM base + * edx: Temp RAM top + * edi: BIST value + * mm0: low 32-bits of TSC value + * mm1: high 32-bits of TSC value + */ + + cmp $0, %eax + jne halt2 + + /* Setup bootloader stack */ + movl %edx, %esp + + /* + * ebp: FSP_INFO_HEADER address + * ecx: Temp RAM base + * edx: Temp RAM top + * edi: BIST value + * esp: Top of stack in temp RAM + * mm0: low 32-bits of TSC value + * mm1: high 32-bits of TSC value + */ + + /* Create cache_as_ram_params on stack */ + pushl %edx /* bootloader CAR end */ + pushl %ecx /* bootloader CAR begin */ + pushl %ebp /* FSP_INFO_HEADER */ + pushl %edi /* bist */ + movd %mm1, %eax + pushl %eax /* tsc[63:32] */ + movd %mm0, %eax + pushl %eax /* tsc[31:0] */ + pushl %esp /* pointer to cache_as_ram_params */ + + /* Save FSP_INFO_HEADER location in ebx */ + mov %ebp, %ebx + + /* coreboot assumes stack/heap region will be zero */ + cld + movl %ecx, %edi + neg %ecx + /* Only clear up to current stack value. */ + add %esp, %ecx + shrl $2, %ecx + xorl %eax, %eax + rep stosl + + /* Restore the timestamp from bootblock_crt0.S (ebp:mm1) */ + push %ebp + movd %mm1, %eax + push %eax + + /* We can call into C functions now */ + call bootblock_c_entry + + /* Never reached */ + +halt1: + /* + * Failures for postcode 0xBA - failed in fsp_fih_early_find() + * + * Values are: + * 0x01 - FV signature, "_FVH" not present + * 0x02 - FFS GUID not present + * 0x03 - FSP INFO Header not found + * 0x04 - ImageBase does not equal CONFIG_FSP_LOC - Is the FSP + rebased to a different location, or does it need to be? + * 0x05 - FSP INFO Header signature "FSPH" not found + * 0x06 - FSP Image ID is not the expected ID. + */ + movb $0xBA, %ah + jmp .Lhlt + +halt2: + /* + * Failures for postcode 0xBB - failed in the FSP: + * + * 0x00 - FSP_SUCCESS: Temp RAM was initialized successfully. + * 0x02 - FSP_INVALID_PARAMETER: Input parameters are invalid. + * 0x03 - FSP_UNSUPPORTED: The FSP calling conditions were not met. + * 0x07 - FSP_DEVICE_ERROR: Temp RAM initialization failed + * 0x0E - FSP_NOT_FOUND: No valid microcode was found in the microcode region. + * 0x14 - FSP_ALREADY_STARTED: Temp RAM initialization has been invoked + */ + movb $0xBB, %ah + jmp .Lhlt + +.Lhlt: + xchg %al, %ah +#if IS_ENABLED(CONFIG_POST_IO) + outb %al, $CONFIG_POST_IO_PORT +#else + post_code(POST_DEAD_CODE) +#endif + movl $LHLT_DELAY, %ecx +.Lhlt_Delay: + outb %al, $0xED + loop .Lhlt_Delay + jmp .Lhlt + +/* + * esp is set to this location so that the call into and return from the FSP + * in find_fsp will work. + */ + .align 4 +fake_fsp_stack: + .long find_fsp_ret + .long CONFIG_FSP_LOC /* FSP base address */ + +CAR_init_params: + .long CONFIG_CPU_MICROCODE_CBFS_LOC /* Microcode Location */ + .long CONFIG_CPU_MICROCODE_CBFS_LEN /* Microcode Length */ + .long 0xFFFFFFFF - CONFIG_ROM_SIZE + 1 /* Firmware Location */ + .long CONFIG_ROM_SIZE /* Total FW Length */ + +CAR_init_stack: + .long CAR_init_done + .long CAR_init_params diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index 50c2802..e7b0ef7 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -40,15 +40,30 @@ select TSC_MONOTONIC_TIMER select TSC_SYNC_MFENCE select UDELAY_TSC - select USE_GENERIC_FSP_CAR_INC select INTEL_DESCRIPTOR_MODE_CAPABLE select HAVE_SPI_CONSOLE_SUPPORT select HAVE_FSP_GOP select GENERIC_GPIO_LIB select INTEL_GMA_ACPI select INTEL_GMA_SWSMISCI + select BOOTBLOCK_CONSOLE select CPU_INTEL_COMMON
+config USE_GENERIC_FSP_CAR_INC + bool + default y if !C_ENVIRONMENT_BOOTBLOCK + +config DCACHE_BSP_STACK_SIZE + hex + default 0x2000 + help + The amount of anticipated stack usage in CAR by bootblock and + other stages. + +config C_ENV_BOOTBLOCK_SIZE + hex + default 0x8000 + config VBOOT select VBOOT_STARTS_IN_ROMSTAGE
diff --git a/src/soc/intel/braswell/Makefile.inc b/src/soc/intel/braswell/Makefile.inc index ac1bacd..6939ddd 100644 --- a/src/soc/intel/braswell/Makefile.inc +++ b/src/soc/intel/braswell/Makefile.inc @@ -9,6 +9,8 @@ subdirs-y += ../../../cpu/intel/turbo subdirs-y += ../../../cpu/intel/common
+bootblock-$(CONFIG_C_ENVIRONMENT_BOOTBLOCK) += bootblock/bootblock_c.c + romstage-y += gpio_support.c romstage-y += iosf.c romstage-y += lpc_init.c diff --git a/src/soc/intel/braswell/bootblock/bootblock_c.c b/src/soc/intel/braswell/bootblock/bootblock_c.c new file mode 100644 index 0000000..8cb6fa8 --- /dev/null +++ b/src/soc/intel/braswell/bootblock/bootblock_c.c @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootblock_common.h> +#include <console/console.h> +#include <fsp/bootblock.h> + +asmlinkage void bootblock_c_entry(uint64_t base_timestamp) +{ + /* Call lib/bootblock.c main */ + bootblock_main_with_timestamp(base_timestamp, NULL, 0); +} + +void bootblock_soc_early_init(void) +{ +} + + +void bootblock_soc_init(void) +{ + printk(BIOS_DEBUG, "FSP TempRamInit successful\n"); +} diff --git a/src/soc/intel/braswell/include/soc/bootblock.h b/src/soc/intel/braswell/include/soc/bootblock.h new file mode 100644 index 0000000..072e55d --- /dev/null +++ b/src/soc/intel/braswell/include/soc/bootblock.h @@ -0,0 +1,19 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_BOOTBLOCK_H_ +#define _SOC_BOOTBLOCK_H_ + +#endif /* _SOC_BOOTBLOCK_H_ */ diff --git a/src/soc/intel/braswell/romstage/Makefile.inc b/src/soc/intel/braswell/romstage/Makefile.inc index c3ed415..7afb0b5 100644 --- a/src/soc/intel/braswell/romstage/Makefile.inc +++ b/src/soc/intel/braswell/romstage/Makefile.inc @@ -1,3 +1,4 @@ +romstage-$(CONFIG_C_ENVIRONMENT_BOOTBLOCK) += car_stage.S romstage-y += early_spi.c romstage-y += pmc.c romstage-y += romstage.c diff --git a/src/soc/intel/braswell/romstage/car_stage.S b/src/soc/intel/braswell/romstage/car_stage.S new file mode 100644 index 0000000..db9f404 --- /dev/null +++ b/src/soc/intel/braswell/romstage/car_stage.S @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc + * Copyright 2018 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* I/O delay between post codes on failure */ +#define LHLT_DELAY 0x50000 + +.text +.global car_stage_entry +car_stage_entry: + call romstage_c_entry + #include "src/drivers/intel/fsp1_1/after_raminit.S" + + movb $0x69, %ah + jmp .Lhlt + +.Lhlt: + xchg %al, %ah +#if IS_ENABLED(CONFIG_POST_IO) + outb %al, $CONFIG_POST_IO_PORT +#else + post_code(POST_DEAD_CODE) +#endif + movl $LHLT_DELAY, %ecx +.Lhlt_Delay: + outb %al, $0xED + loop .Lhlt_Delay + jmp .Lhlt
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Frans Hendriks (Code Review)