Change in coreboot[master]: soc/intel/baytrail,broadwell: Use bootstate for save_wake_source()

[Kyösti Mälkki (Code Review)]

Attention is currently required from: Patrick Rudolph.
Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49818 )

Change subject: soc/intel/baytrail,broadwell: Use bootstate for save_wake_source()
......................................................................

soc/intel/baytrail,broadwell: Use bootstate for save_wake_source()

Change-Id: I01be1b9dfefcfcf037de4153e9540c7258dc160f
Signed-off-by: Kyösti Mälkki 
---
M src/soc/intel/baytrail/ramstage.c
M src/soc/intel/broadwell/ramstage.c
2 files changed, 32 insertions(+), 20 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/49818/1

diff --git a/src/soc/intel/baytrail/ramstage.c b/src/soc/intel/baytrail/ramstage.c
index 0c955e3..0888645 100644
--- a/src/soc/intel/baytrail/ramstage.c
+++ b/src/soc/intel/baytrail/ramstage.c
@@ -117,15 +117,8 @@
 }

/* Save bit index for first enabled event in PM1_STS for _SB._SWS */
-static void save_acpi_wake_source(void)
 {
-	struct chipset_power_state *ps = acpi_get_pm_state();
-	struct global_nvs *gnvs = acpi_get_gnvs();
    uint16_t pm1;
-
-	if (!ps || !gnvs)
-		return;
-
    pm1 = ps->pm1_sts & ps->pm1_en;

/* Scan for first set bit in PM1 */
@@ -143,6 +136,21 @@
           gnvs->pm1i);
 }

+static void acpi_save_wake_source(void *unused)
+{
+	const struct chipset_power_state *ps;
+	struct global_nvs *gnvs = acpi_get_gnvs();
+	if (!gnvs)
+		return;
+
+	if (acpi_pm_state_for_wake(&ps) < 0)
+		return;
+
+	save_wake_source(gnvs);
+}
+
+BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, acpi_save_wake_source, NULL);
+
 static void baytrail_enable_2x_refresh_rate(void)
 {
    u32 reg;
@@ -164,10 +172,6 @@
    /* Allow for SSE instructions to be executed. */
    write_cr4(read_cr4() | CR4_OSFXSR | CR4_OSXMMEXCPT);

-	/* Indicate S3 resume to rest of ramstage. */
-	if (acpi_is_wakeup_s3())
-		save_acpi_wake_source();
-
    /* Run reference code. */
    baytrail_run_reference_code();

diff --git a/src/soc/intel/broadwell/ramstage.c b/src/soc/intel/broadwell/ramstage.c
index 93bc01d..dfa8e00 100644
--- a/src/soc/intel/broadwell/ramstage.c
+++ b/src/soc/intel/broadwell/ramstage.c
@@ -3,6 +3,7 @@
 #include <acpi/acpi.h>
 #include <acpi/acpi_gnvs.h>
 #include <acpi/acpi_pm.h>
+#include <bootstate.h>
 #include <console/console.h>
 #include <device/device.h>
 #include <string.h>
@@ -12,16 +13,11 @@
 #include <soc/intel/broadwell/chip.h>

/* Save bit index for PM1_STS and GPE_STS for ACPI _SWS */
-static void save_acpi_wake_source(void)
+static void save_wake_source(const struct chipset_power_state *ps, struct global_nvs *gnvs)
 {
-	struct chipset_power_state *ps = acpi_get_pm_state();
-	struct global_nvs *gnvs = acpi_get_gnvs();
    uint16_t pm1;
    int gpe_reg;

-	if (!ps || !gnvs)
-		return;
-
    pm1 = ps->pm1_sts & ps->pm1_en;

/* Scan for first set bit in PM1 */
@@ -63,10 +59,22 @@
           gnvs->pm1i, gnvs->gpei);
 }

+static void acpi_save_wake_source(void *unused)
+{
+	const struct chipset_power_state *ps;
+	struct global_nvs *gnvs = acpi_get_gnvs();
+	if (!gnvs)
+		return;
+
+	if (acpi_pm_state_for_wake(&ps) < 0)
+		return;
+
+	save_wake_source(ps, gnvs);
+}
+
+BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, acpi_save_wake_source, NULL);
+
 void broadwell_init_pre_device(void *chip_info)
 {
-	if (acpi_is_wakeup_s3())
-		save_acpi_wake_source();
-
    broadwell_run_reference_code();
 }