Change in coreboot[master]: [WIP] soc/amd/cezanne: select ACPI support and make the compiler happy

[Felix Held (Code Review)]

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50273 )

Change subject: [WIP] soc/amd/cezanne: select ACPI support and make the compiler happy
......................................................................

[WIP] soc/amd/cezanne: select ACPI support and make the compiler happy

This isn't meant to be submitted in the current state.

Signed-off-by: Felix Held 
Change-Id: I9b806569154e46418fa7d4fa35575a0acfec9132
---
A src/mainboard/amd/majolica/dsdt.asl
A src/mainboard/google/guybrush/dsdt.asl
M src/soc/amd/cezanne/Kconfig
M src/soc/amd/cezanne/Makefile.inc
A src/soc/amd/cezanne/acpi.c
A src/soc/amd/cezanne/include/soc/acpi.h
A src/soc/amd/cezanne/include/soc/nvs.h
M src/soc/amd/cezanne/include/soc/southbridge.h
8 files changed, 124 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/50273/1

diff --git a/src/mainboard/amd/majolica/dsdt.asl b/src/mainboard/amd/majolica/dsdt.asl
new file mode 100644
index 0000000..637a6e5
--- /dev/null
+++ b/src/mainboard/amd/majolica/dsdt.asl
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#define MAINBOARD_HAS_SPEAKER 1
+
+/* DefinitionBlock Statement */
+#include <acpi/acpi.h>
+DefinitionBlock (
+	"dsdt.aml",
+	"DSDT",
+	ACPI_DSDT_REV_2,
+	OEM_ID,
+	ACPI_TABLE_CREATOR,
+	0x00010001	/* OEM Revision */
+	)
+{	/* Start of ASL file */
+	#include <acpi/dsdt_top.asl>
+
+	/* System Bus */
+	Scope(_SB) { /* Start _SB scope */
+		/* global utility methods expected within the _SB scope */
+		#include <arch/x86/acpi/globutil.asl>
+
+	} /* End _SB scope */
+}
+/* End of ASL file */
+
diff --git a/src/mainboard/google/guybrush/dsdt.asl b/src/mainboard/google/guybrush/dsdt.asl
new file mode 100644
index 0000000..5b24c2e
--- /dev/null
+++ b/src/mainboard/google/guybrush/dsdt.asl
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/* DefinitionBlock Statement */
+#include <acpi/acpi.h>
+DefinitionBlock (
+	"dsdt.aml",
+	"DSDT",
+	ACPI_DSDT_REV_2,
+	OEM_ID,
+	ACPI_TABLE_CREATOR,
+	0x00010001	/* OEM Revision */
+	)
+{	/* Start of ASL file */
+	#include <acpi/dsdt_top.asl>
+
+	/* System Bus */
+	Scope(_SB) { /* Start _SB scope */
+		/* global utility methods expected within the _SB scope */
+		#include <arch/x86/acpi/globutil.asl>
+
+	} /* End _SB scope */
+}
+/* End of ASL file */
+
diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig
index 611260d..3d6d23a 100644
--- a/src/soc/amd/cezanne/Kconfig
+++ b/src/soc/amd/cezanne/Kconfig
@@ -13,14 +13,17 @@
    select ARCH_VERSTAGE_X86_32
    select ARCH_ROMSTAGE_X86_32
    select ARCH_RAMSTAGE_X86_32
+	select ACPI_AMD_HARDWARE_SLEEP_VALUES
    select FSP_COMPRESS_FSP_M_LZMA
    select FSP_COMPRESS_FSP_S_LZMA
+	select HAVE_ACPI_TABLES
    select HAVE_CF9_RESET
    select IDT_IN_EVERY_STAGE
    select IOAPIC
    select PLATFORM_USES_FSP2_0
    select RESET_VECTOR_IN_RAM
    select SOC_AMD_COMMON
+	select SOC_AMD_COMMON_BLOCK_ACPI
    select SOC_AMD_COMMON_BLOCK_ACPIMMIO
    select SOC_AMD_COMMON_BLOCK_AOAC
    select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS
diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc
index 9422a4d..e91e792 100644
--- a/src/soc/amd/cezanne/Makefile.inc
+++ b/src/soc/amd/cezanne/Makefile.inc
@@ -24,6 +24,7 @@
 romstage-y	+= romstage.c
 romstage-y	+= uart.c

+ramstage-y	+= acpi.c
 ramstage-y	+= chip.c
 ramstage-y	+= fch.c
 ramstage-y      += fsp_params.c
diff --git a/src/soc/amd/cezanne/acpi.c b/src/soc/amd/cezanne/acpi.c
new file mode 100644
index 0000000..a80b426
--- /dev/null
+++ b/src/soc/amd/cezanne/acpi.c
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/* ACPI - create the Fixed ACPI Description Tables (FADT) */
+
+#include <acpi/acpi.h>
+
+unsigned long acpi_fill_mcfg(unsigned long current)
+{
+
+	current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current,
+					     CONFIG_MMCONF_BASE_ADDRESS,
+					     0,
+					     0,
+					     CONFIG_MMCONF_BUS_NUMBER - 1);
+
+	return current;
+}
+
+unsigned long acpi_fill_madt(unsigned long current)
+{
+	/* TODO */
+	return 0;
+}
+
+/*
+ * Reference section 5.2.9 Fixed ACPI Description Table (FADT)
+ * in the ACPI 3.0b specification.
+ */
+void acpi_fill_fadt(acpi_fadt_t *fadt)
+{
+	/* TODO */
+}
+
diff --git a/src/soc/amd/cezanne/include/soc/acpi.h b/src/soc/amd/cezanne/include/soc/acpi.h
new file mode 100644
index 0000000..68b64aa
--- /dev/null
+++ b/src/soc/amd/cezanne/include/soc/acpi.h
@@ -0,0 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef AMD_CEZANNE_ACPI_H
+#define AMD_CEZANNE_ACPI_H
+
+#endif /* AMD_CEZANNE_ACPI_H */
diff --git a/src/soc/amd/cezanne/include/soc/nvs.h b/src/soc/amd/cezanne/include/soc/nvs.h
new file mode 100644
index 0000000..07053d5
--- /dev/null
+++ b/src/soc/amd/cezanne/include/soc/nvs.h
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+/*
+ * NOTE: The layout of the global_nvs structure below must match the layout
+ * in soc/soc/amd/picasso/acpi/globalnvs.asl !!!
+ *
+ */
+
+#ifndef AMD_CEZANNE_NVS_H
+#define AMD_CEZANNE_NVS_H
+
+#include <stdint.h>
+
+struct __packed global_nvs {
+	/* Miscellaneous */
+	uint8_t		unused_was_pcnt; /* 0x00 - Processor Count */
+	uint8_t		lids; /* 0x01 - LID State */
+	uint8_t		pwrs; /* 0x02 - AC Power State */
+	uint32_t	cbmc; /* 0x03 - 0x06 - coreboot Memory Console */
+	uint64_t	pm1i; /* 0x07 - 0x0e - System Wake Source - PM1 Index */
+	uint64_t	gpei; /* 0x0f - 0x16 - GPE Wake Source */
+	uint8_t		tmps; /* 0x17 - Temperature Sensor ID */
+	uint8_t		tcrt; /* 0x18 - Critical Threshold */
+	uint8_t		tpsv; /* 0x19 - Passive Threshold */
+};
+
+#endif /* AMD_CEZANNE_NVS_H */
diff --git a/src/soc/amd/cezanne/include/soc/southbridge.h b/src/soc/amd/cezanne/include/soc/southbridge.h
index 8623063..f644f78 100644
--- a/src/soc/amd/cezanne/include/soc/southbridge.h
+++ b/src/soc/amd/cezanne/include/soc/southbridge.h
@@ -40,6 +40,10 @@
 #define   PM_ACPI_NB_PME_GEVENT		BIT(28)
 #define   PM_ACPI_RTC_WAKE_EN		BIT(29)

+#define PM1_LIMIT			16
+#define GPE0_LIMIT			32
+#define TOTAL_BITS(a)			(8 * sizeof(a))
+
 #define FCH_LEGACY_UART_DECODE		(ALINK_AHB_ADDRESS + 0x20) /* 0xfedc0020 */

/* FCH AOAC device offsets for AOAC_DEV_D3_CTL/AOAC_DEV_D3_STATE */