Change in coreboot[master]: soc/mediatek/mt8186: Change the power-down time slot from 0xA to 0xF

[Rex-BC Chen (Code Review)]

Attention is currently required from: Hung-Te Lin, Rex-BC Chen, Paul Menzel.
Hello Hung-Te Lin, build bot (Jenkins), Yu-Ping Wu,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/64038

to look at the new patch set (#4).

Change subject: soc/mediatek/mt8186: Change the power-down time slot from 0xA to 0xF
......................................................................

soc/mediatek/mt8186: Change the power-down time slot from 0xA to 0xF

PMIC_CPSDSA4[4:0] controls the power-down at the specified time slot.
Setting it to 0xA would cause an extra delay of 20ms compared to 0xF.
The value of time slot is from 0x0 to 0x1F which represents the delay
when reset occurs.

To avoid the delay, change the value from 0xA to 0xF.

This modification is based on chapter 3.7 in the MT8186 functional
specification.

BUG=b:218630683, b:218630684
TEST=the power-off waveform is correct.

Signed-off-by: zhiyong tao 
Change-Id: I537fe87740f0f8c25b923d7d536e81503b71762b
---
M src/soc/mediatek/mt8186/mt6366.c
1 file changed, 2 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/64038/4