Change in coreboot[master]: sb/amd/cimx/sb800/acpi: Convert 'smbus.asl' to ASL 2.0 syntax

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HAOUAS Elyes (Code Review)

30 Sep 2020 30 Sep '20

7:21 p.m.

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45875 )

Change subject: sb/amd/cimx/sb800/acpi: Convert 'smbus.asl' to ASL 2.0 syntax ......................................................................

sb/amd/cimx/sb800/acpi: Convert 'smbus.asl' to ASL 2.0 syntax

Also, fix typo on "success".

Change-Id: I6fd7056d8053f0097b5c9de6b4e2e6db38910a2e Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/southbridge/amd/cimx/sb800/acpi/smbus.asl 1 file changed, 31 insertions(+), 31 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/45875/1

diff --git a/src/southbridge/amd/cimx/sb800/acpi/smbus.asl b/src/southbridge/amd/cimx/sb800/acpi/smbus.asl index a676893..b99da33 100644 --- a/src/southbridge/amd/cimx/sb800/acpi/smbus.asl +++ b/src/southbridge/amd/cimx/sb800/acpi/smbus.asl @@ -19,37 +19,37 @@ }

Method (WCLR, 0, NotSerialized) { /* clear SMBUS status register */ - Store (0x1E, HSTS) - Store (0xFA, Local0) - While (LAnd (LNotEqual (And (HSTS, 0x1E), Zero), LGreater (Local0, Zero))) { + HSTS = 0x1E + Local0 = 0xFA + While ((HSTS & 0x1E) != Zero) && (Local0 > 0)) { Stall (0x64) - Decrement (Local0) + Local0-- }

Return (Local0) }

Method (SWTC, 1, NotSerialized) { - Store (Arg0, Local0) - Store (0x07, Local2) - Store (One, Local1) - While (LEqual (Local1, One)) { - Store (And (HSTS, 0x1E), Local3) - If (LNotEqual (Local3, Zero)) { /* read sucess */ - If (LEqual (Local3, 0x02)) { - Store (Zero, Local2) + Local0 = Arg0 + Local2 = 0x07 + Local1 = 1 + While (Local1 == 1) { + Local3 = HSTS & 0x1E + If (Local3 != 0) { /* read success */ + If (Local3 != 0x02) { + Local2 = 0 }

- Store (Zero, Local1) + Local1 = 0 } Else { - If (LLess (Local0, 0x0A)) { /* read failure */ - Store (0x10, Local2) - Store (Zero, Local1) + If (Local0 < 0x0A) { /* read failure */ + Local2 = 0x10 + Local1 = 0 } Else { Sleep (0x0A) /* 10 ms, try again */ - Subtract (Local0, 0x0A, Local0) + Local0 -= 0x0A } } } @@ -58,29 +58,29 @@ }

Method (SMBR, 3, NotSerialized) { - Store (0x07, Local0) - If (LEqual (Acquire (SBX0, 0xFFFF), Zero)) { - Store (WCLR (), Local0) /* clear SMBUS status register before read data */ - If (LEqual (Local0, Zero)) { + Local0 = 0x07 + If (Acquire (SBX0, 0xFFFF) == 0) { + Local0 = WCLR () /* clear SMBUS status register before read data */ + If (Local0 == 0) { Release (SBX0) Return (0x0) }

- Store (0x1F, HSTS) - Store (Or (ShiftLeft (Arg1, One), One), HADD) - Store (Arg2, HCMD) - If (LEqual (Arg0, 0x07)) { - Store (0x48, HCNT) /* read byte */ + HSTS = 0x1F + HADD = (Arg1 << 1) | 1 + HCMD = Arg2 + If (Arg0 == 0x07) { + HCNT = 0x48 /* read byte */ }

- Store (SWTC (0x03E8), Local1) /* 1000 ms */ - If (LEqual (Local1, Zero)) { - If (LEqual (Arg0, 0x07)) { - Store (DAT0, Local0) + Local1 = SWTC (0x03E8) /* 1000 ms */ + If (Local1 == 0) { + If (Arg0 == 0x07) { + Local0 = DAT0 } } Else { - Store (Local1, Local0) + Local0 = Local1 }

Release (SBX0)

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HAOUAS Elyes (Code Review)

2 Oct 2 Oct

9:50 a.m.

Hello build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/45875

to look at the new patch set (#2).

Change subject: sb/amd/cimx/sb800/acpi: Convert 'smbus.asl' to ASL 2.0 syntax ......................................................................

sb/amd/cimx/sb800/acpi: Convert 'smbus.asl' to ASL 2.0 syntax

Also, fix typo on "success".

Change-Id: I6fd7056d8053f0097b5c9de6b4e2e6db38910a2e Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/southbridge/amd/cimx/sb800/acpi/smbus.asl 1 file changed, 31 insertions(+), 31 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/45875/2

HAOUAS Elyes (Code Review)

27 Jan 27 Jan

11:29 a.m.

Hello build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/45875

to look at the new patch set (#3).

Change subject: sb/amd/cimx/sb800/acpi: Convert 'smbus.asl' to ASL 2.0 syntax ......................................................................

sb/amd/cimx/sb800/acpi: Convert 'smbus.asl' to ASL 2.0 syntax

Also, fix typo on "success". Built gizmosphere/gizmo generate identical 'build/dsdt.dsl'.

Change-Id: I6fd7056d8053f0097b5c9de6b4e2e6db38910a2e Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/southbridge/amd/cimx/sb800/acpi/fch.asl M src/southbridge/amd/cimx/sb800/acpi/pcie.asl M src/southbridge/amd/cimx/sb800/acpi/smbus.asl 3 files changed, 119 insertions(+), 119 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/45875/3

HAOUAS Elyes (Code Review)

11:40 a.m.

Hello build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/45875

to look at the new patch set (#4).

Change subject: sb/amd/cimx/sb800/acpi: Convert 'smbus.asl' to ASL 2.0 syntax ......................................................................

sb/amd/cimx/sb800/acpi: Convert 'smbus.asl' to ASL 2.0 syntax

Also, fix typo on "success". Built gizmosphere/gizmo generate identical 'build/dsdt.dsl'.

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/45875/4

Kyösti Mälkki (Code Review)

10 Feb 10 Feb

12:14 a.m.

Attention is currently required from: HAOUAS Elyes. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45875 )

Change subject: sb/amd/cimx/sb800/acpi: Convert 'smbus.asl' to ASL 2.0 syntax ......................................................................

Patch Set 4:

(2 comments)

Commit Message:

https://review.coreboot.org/c/coreboot/+/45875/comment/2a6dae01_8a756253 PS4, Line 7: sb/amd/cimx/sb800/acpi: Convert 'smbus.asl' to ASL 2.0 syntax Drop 'smbus.asl'

File src/southbridge/amd/cimx/sb800/acpi/pcie.asl:

https://review.coreboot.org/c/coreboot/+/45875/comment/f2a857a1_bc8a02ae PS4, Line 360: IRQN = 1 << PIRE extra space becore PIRE

-- To view, visit https://review.coreboot.org/c/coreboot/+/45875 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6fd7056d8053f0097b5c9de6b4e2e6db38910a2e Gerrit-Change-Number: 45875 Gerrit-PatchSet: 4 Gerrit-Owner: HAOUAS Elyes ehaouas@noos.fr Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Kyösti Mälkki kyosti.malkki@gmail.com Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-Attention: HAOUAS Elyes ehaouas@noos.fr Gerrit-Comment-Date: Wed, 10 Feb 2021 00:14:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

Kyösti Mälkki (Code Review)

12:47 a.m.

New subject: Change in coreboot[master]: sb/amd/cimx/sb800/acpi: Convert to ASL 2.0 syntax

Attention is currently required from: HAOUAS Elyes. Kyösti Mälkki has uploaded a new patch set (#5) to the change originally created by HAOUAS Elyes. ( https://review.coreboot.org/c/coreboot/+/45875 )

Change subject: sb/amd/cimx/sb800/acpi: Convert to ASL 2.0 syntax ......................................................................

sb/amd/cimx/sb800/acpi: Convert to ASL 2.0 syntax

Also, fix typo on "success". Built gizmosphere/gizmo generate identical 'build/dsdt.dsl'.

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/45875/5

-- To view, visit https://review.coreboot.org/c/coreboot/+/45875 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6fd7056d8053f0097b5c9de6b4e2e6db38910a2e Gerrit-Change-Number: 45875 Gerrit-PatchSet: 5 Gerrit-Owner: HAOUAS Elyes ehaouas@noos.fr Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Kyösti Mälkki kyosti.malkki@gmail.com Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-Attention: HAOUAS Elyes ehaouas@noos.fr Gerrit-MessageType: newpatchset

Kyösti Mälkki (Code Review)

12:51 a.m.

New subject: Change in coreboot[master]: sb/amd/cimx/sb800/acpi: Convert to ASL 2.0 syntax

Attention is currently required from: HAOUAS Elyes. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45875 )

Change subject: sb/amd/cimx/sb800/acpi: Convert to ASL 2.0 syntax ......................................................................

Patch Set 5:

(2 comments)

Commit Message:

https://review.coreboot.org/c/coreboot/+/45875/comment/83ea86d4_94de7753 PS4, Line 7: sb/amd/cimx/sb800/acpi: Convert 'smbus.asl' to ASL 2.0 syntax

...

Drop 'smbus. […]

Done

File src/southbridge/amd/cimx/sb800/acpi/pcie.asl:

https://review.coreboot.org/c/coreboot/+/45875/comment/b63f28be_be85bfae PS4, Line 360: IRQN = 1 << PIRE

...

extra space becore PIRE

Done

-- To view, visit https://review.coreboot.org/c/coreboot/+/45875 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6fd7056d8053f0097b5c9de6b4e2e6db38910a2e Gerrit-Change-Number: 45875 Gerrit-PatchSet: 5 Gerrit-Owner: HAOUAS Elyes ehaouas@noos.fr Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Kyösti Mälkki kyosti.malkki@gmail.com Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-Attention: HAOUAS Elyes ehaouas@noos.fr Gerrit-Comment-Date: Wed, 10 Feb 2021 00:51:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kyösti Mälkki kyosti.malkki@gmail.com Gerrit-MessageType: comment

Kyösti Mälkki (Code Review)

1:07 a.m.

New subject: Change in coreboot[master]: sb/amd/cimx/sb800/acpi: Convert to ASL 2.0 syntax

Attention is currently required from: HAOUAS Elyes. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45875 )

Change subject: sb/amd/cimx/sb800/acpi: Convert to ASL 2.0 syntax ......................................................................

Patch Set 5: Code-Review+2

-- To view, visit https://review.coreboot.org/c/coreboot/+/45875 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6fd7056d8053f0097b5c9de6b4e2e6db38910a2e Gerrit-Change-Number: 45875 Gerrit-PatchSet: 5 Gerrit-Owner: HAOUAS Elyes ehaouas@noos.fr Gerrit-Reviewer: Kyösti Mälkki kyosti.malkki@gmail.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-Attention: HAOUAS Elyes ehaouas@noos.fr Gerrit-Comment-Date: Wed, 10 Feb 2021 01:07:46 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

Angel Pons (Code Review)

3:04 a.m.

New subject: Change in coreboot[master]: sb/amd/cimx/sb800/acpi: Convert to ASL 2.0 syntax

Attention is currently required from: Kyösti Mälkki, HAOUAS Elyes. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45875 )

Change subject: sb/amd/cimx/sb800/acpi: Convert to ASL 2.0 syntax ......................................................................

Patch Set 5: Code-Review+2

-- To view, visit https://review.coreboot.org/c/coreboot/+/45875 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6fd7056d8053f0097b5c9de6b4e2e6db38910a2e Gerrit-Change-Number: 45875 Gerrit-PatchSet: 5 Gerrit-Owner: HAOUAS Elyes ehaouas@noos.fr Gerrit-Reviewer: Angel Pons th3fanbus@gmail.com Gerrit-Reviewer: Kyösti Mälkki kyosti.malkki@gmail.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-Attention: Kyösti Mälkki kyosti.malkki@gmail.com Gerrit-Attention: HAOUAS Elyes ehaouas@noos.fr Gerrit-Comment-Date: Wed, 10 Feb 2021 03:04:02 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

Kyösti Mälkki (Code Review)

9:25 a.m.

New subject: Change in coreboot[master]: sb/amd/cimx/sb800/acpi: Convert to ASL 2.0 syntax

Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45875 )

Change subject: sb/amd/cimx/sb800/acpi: Convert to ASL 2.0 syntax ......................................................................

sb/amd/cimx/sb800/acpi: Convert to ASL 2.0 syntax

Also, fix typo on "success". Built gizmosphere/gizmo generate identical 'build/dsdt.dsl'.

Change-Id: I6fd7056d8053f0097b5c9de6b4e2e6db38910a2e Signed-off-by: Elyes HAOUAS ehaouas@noos.fr Reviewed-on: https://review.coreboot.org/c/coreboot/+/45875 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Kyösti Mälkki kyosti.malkki@gmail.com Reviewed-by: Angel Pons th3fanbus@gmail.com --- M src/southbridge/amd/cimx/sb800/acpi/fch.asl M src/southbridge/amd/cimx/sb800/acpi/pcie.asl M src/southbridge/amd/cimx/sb800/acpi/smbus.asl 3 files changed, 118 insertions(+), 118 deletions(-)

Approvals: build bot (Jenkins): Verified Kyösti Mälkki: Looks good to me, approved Angel Pons: Looks good to me, approved

diff --git a/src/southbridge/amd/cimx/sb800/acpi/fch.asl b/src/southbridge/amd/cimx/sb800/acpi/fch.asl index a3a17a4..59b556b 100644 --- a/src/southbridge/amd/cimx/sb800/acpi/fch.asl +++ b/src/southbridge/amd/cimx/sb800/acpi/fch.asl @@ -7,23 +7,23 @@ Method(_OSC,4) { /* Check for proper PCI/PCIe UUID */ - If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) + If (Arg0 == ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")) { /* Let OS control everything */ Return (Arg3) } Else { CreateDWordField(Arg3,0,CDW1) - Or(CDW1,4,CDW1) // Unrecognized UUID - Return(Arg3) + CDW1 |= 4 // Unrecognized UUID + Return (Arg3) } }

Method(_BBN, 0) { /* Bus number = 0 */ - Return(0) + Return (0) } Method(_STA, 0) { /* DBGO("\_SB\PCI0\_STA\n") */ - Return(0x0B) /* Status is visible */ + Return (0x0b) /* Status is visible */ }

Method(_PRT,0) { @@ -126,12 +126,12 @@ * 32bit (0x00000000 - TOM1) will wrap and give the same * result as 64bit (0x100000000 - TOM1). */ - Store(TOM1, MM1B) - ShiftLeft(0x10000000, 4, Local0) - Subtract(Local0, TOM1, Local0) - Store(Local0, MM1L) + MM1B = TOM1 + Local0 = 0x10000000 << 4 + Local0 -= TOM1 + MM1L = Local0

- Return(CRES) /* note to change the Name buffer */ + Return (CRES) /* note to change the Name buffer */ } /* end of Method(_SB.PCI0._CRS) */

/* @@ -160,8 +160,8 @@ OSFL()

/* On older chips, clear PciExpWakeDisEn */ - /*if (LLessEqual(\SBRI, 0x13)) { - * Store(0,\PWDE) + /*if (\SBRI <= 0x13) { + * \PWDE = 0 * } */ } /* End Method(_SB._INI) */ @@ -173,10 +173,10 @@ CMTI, 8, /* Client Management Data register */ G64E, 1, - G64O, 1, - G32O, 2, + G64O, 1, + G32O, 2, , 2, - GPSL, 2, + GPSL, 2, }

/* GPM Port register */ diff --git a/src/southbridge/amd/cimx/sb800/acpi/pcie.asl b/src/southbridge/amd/cimx/sb800/acpi/pcie.asl index 4420938..a154fd8 100644 --- a/src/southbridge/amd/cimx/sb800/acpi/pcie.asl +++ b/src/southbridge/amd/cimx/sb800/acpi/pcie.asl @@ -138,18 +138,18 @@ { _SB.CIRQ() } - Store(Arg0, PICM) + PICM = Arg0 }

Method(CIRQ, 0x00, NotSerialized){ - Store(0, PIRA) - Store(0, PIRB) - Store(0, PIRC) - Store(0, PIRD) - Store(0, PIRE) - Store(0, PIRF) - Store(0, PIRG) - Store(0, PIRH) + PIRA = 0 + PIRB = 0 + PIRC = 0 + PIRD = 0 + PIRE = 0 + PIRF = 0 + PIRG = 0 + PIRH = 0 }

Name(IRQB, ResourceTemplate(){ @@ -170,27 +170,27 @@

Method(_STA, 0) { if (PIRA) { - Return(0x0B) /* sata is invisible */ + Return (0x0b) /* sata is invisible */ } else { - Return(0x09) /* sata is disabled */ + Return (0x09) /* sata is disabled */ } } /* End Method(_SB.INTA._STA) */

Method(_DIS ,0) { /* DBGO("\_SB\LNKA\_DIS\n") */ - Store(0, PIRA) + PIRA = 0 } /* End Method(_SB.INTA._DIS) */

Method(_PRS ,0) { /* DBGO("\_SB\LNKA\_PRS\n") */ - Return(IRQP) + Return (IRQP) } /* Method(_SB.INTA._PRS) */

Method(_CRS ,0) { /* DBGO("\_SB\LNKA\_CRS\n") */ CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRA, IRQN) - Return(IRQB) + IRQN = 1 << PIRA + Return (IRQB) } /* Method(_SB.INTA._CRS) */

Method(_SRS, 1) { @@ -200,9 +200,9 @@ /* Use lowest available IRQ */ FindSetRightBit(IRQM, Local0) if (Local0) { - Decrement(Local0) + Local0-- } - Store(Local0, PIRA) + PIRA = Local0 } /* End Method(_SB.INTA._SRS) */ } /* End Device(INTA) */

@@ -212,27 +212,27 @@

Method(_STA, 0) { if (PIRB) { - Return(0x0B) /* sata is invisible */ + Return (0x0b) /* sata is invisible */ } else { - Return(0x09) /* sata is disabled */ + Return (0x09) /* sata is disabled */ } } /* End Method(_SB.INTB._STA) */

Method(_DIS ,0) { /* DBGO("\_SB\LNKB\_DIS\n") */ - Store(0, PIRB) + PIRB = 0 } /* End Method(_SB.INTB._DIS) */

Method(_PRS ,0) { /* DBGO("\_SB\LNKB\_PRS\n") */ - Return(IRQP) + Return (IRQP) } /* Method(_SB.INTB._PRS) */

Method(_CRS ,0) { /* DBGO("\_SB\LNKB\_CRS\n") */ CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRB, IRQN) - Return(IRQB) + IRQN = 1 << PIRB + Return (IRQB) } /* Method(_SB.INTB._CRS) */

Method(_SRS, 1) { @@ -242,9 +242,9 @@ /* Use lowest available IRQ */ FindSetRightBit(IRQM, Local0) if (Local0) { - Decrement(Local0) + Local0-- } - Store(Local0, PIRB) + PIRB = Local0 } /* End Method(_SB.INTB._SRS) */ } /* End Device(INTB) */

@@ -254,15 +254,15 @@

Method(_STA, 0) { if (PIRC) { - Return(0x0B) /* sata is invisible */ + Return (0x0b) /* sata is invisible */ } else { - Return(0x09) /* sata is disabled */ + Return (0x09) /* sata is disabled */ } } /* End Method(_SB.INTC._STA) */

Method(_DIS ,0) { /* DBGO("\_SB\LNKC\_DIS\n") */ - Store(0, PIRC) + PIRC = 0 } /* End Method(_SB.INTC._DIS) */

Method(_PRS ,0) { @@ -273,8 +273,8 @@ Method(_CRS ,0) { /* DBGO("\_SB\LNKC\_CRS\n") */ CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRC, IRQN) - Return(IRQB) + IRQN = 1 << PIRC + Return (IRQB) } /* Method(_SB.INTC._CRS) */

Method(_SRS, 1) { @@ -284,9 +284,9 @@ /* Use lowest available IRQ */ FindSetRightBit(IRQM, Local0) if (Local0) { - Decrement(Local0) + Local0-- } - Store(Local0, PIRC) + PIRC = Local0 } /* End Method(_SB.INTC._SRS) */ } /* End Device(INTC) */

@@ -296,27 +296,27 @@

Method(_STA, 0) { if (PIRD) { - Return(0x0B) /* sata is invisible */ + Return (0x0b) /* sata is invisible */ } else { - Return(0x09) /* sata is disabled */ + Return (0x09) /* sata is disabled */ } } /* End Method(_SB.INTD._STA) */

Method(_DIS ,0) { /* DBGO("\_SB\LNKD\_DIS\n") */ - Store(0, PIRD) + PIRD = 0 } /* End Method(_SB.INTD._DIS) */

Method(_PRS ,0) { /* DBGO("\_SB\LNKD\_PRS\n") */ - Return(IRQP) + Return (IRQP) } /* Method(_SB.INTD._PRS) */

Method(_CRS ,0) { /* DBGO("\_SB\LNKD\_CRS\n") */ CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRD, IRQN) - Return(IRQB) + IRQN = 1 << PIRD + Return (IRQB) } /* Method(_SB.INTD._CRS) */

Method(_SRS, 1) { @@ -326,9 +326,9 @@ /* Use lowest available IRQ */ FindSetRightBit(IRQM, Local0) if (Local0) { - Decrement(Local0) + Local0-- } - Store(Local0, PIRD) + PIRD = Local0 } /* End Method(_SB.INTD._SRS) */ } /* End Device(INTD) */

@@ -338,27 +338,27 @@

Method(_STA, 0) { if (PIRE) { - Return(0x0B) /* sata is invisible */ + Return (0x0b) /* sata is invisible */ } else { - Return(0x09) /* sata is disabled */ + Return (0x09) /* sata is disabled */ } } /* End Method(_SB.INTE._STA) */

Method(_DIS ,0) { /* DBGO("\_SB\LNKE\_DIS\n") */ - Store(0, PIRE) + PIRE = 0 } /* End Method(_SB.INTE._DIS) */

Method(_PRS ,0) { /* DBGO("\_SB\LNKE\_PRS\n") */ - Return(IRQP) + Return (IRQP) } /* Method(_SB.INTE._PRS) */

Method(_CRS ,0) { /* DBGO("\_SB\LNKE\_CRS\n") */ CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRE, IRQN) - Return(IRQB) + IRQN = 1 << PIRE + Return (IRQB) } /* Method(_SB.INTE._CRS) */

Method(_SRS, 1) { @@ -368,9 +368,9 @@ /* Use lowest available IRQ */ FindSetRightBit(IRQM, Local0) if (Local0) { - Decrement(Local0) + Local0-- } - Store(Local0, PIRE) + PIRE = Local0 } /* End Method(_SB.INTE._SRS) */ } /* End Device(INTE) */

@@ -380,27 +380,27 @@

Method(_STA, 0) { if (PIRF) { - Return(0x0B) /* sata is invisible */ + Return (0x0b) /* sata is invisible */ } else { - Return(0x09) /* sata is disabled */ + Return (0x09) /* sata is disabled */ } } /* End Method(_SB.INTF._STA) */

Method(_DIS ,0) { /* DBGO("\_SB\LNKF\_DIS\n") */ - Store(0, PIRF) + PIRF = 0 } /* End Method(_SB.INTF._DIS) */

Method(_PRS ,0) { /* DBGO("\_SB\LNKF\_PRS\n") */ - Return(PITF) + Return (PITF) } /* Method(_SB.INTF._PRS) */

Method(_CRS ,0) { /* DBGO("\_SB\LNKF\_CRS\n") */ CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRF, IRQN) - Return(IRQB) + IRQN = 1 << PIRF + Return (IRQB) } /* Method(_SB.INTF._CRS) */

Method(_SRS, 1) { @@ -410,9 +410,9 @@ /* Use lowest available IRQ */ FindSetRightBit(IRQM, Local0) if (Local0) { - Decrement(Local0) + Local0-- } - Store(Local0, PIRF) + PIRF = Local0 } /* End Method(_SB.INTF._SRS) */ } /* End Device(INTF) */

@@ -422,27 +422,27 @@

Method(_STA, 0) { if (PIRG) { - Return(0x0B) /* sata is invisible */ + Return (0x0b) /* sata is invisible */ } else { - Return(0x09) /* sata is disabled */ + Return (0x09) /* sata is disabled */ } } /* End Method(_SB.INTG._STA) */

Method(_DIS ,0) { /* DBGO("\_SB\LNKG\_DIS\n") */ - Store(0, PIRG) + PIRG = 0 } /* End Method(_SB.INTG._DIS) */

Method(_PRS ,0) { /* DBGO("\_SB\LNKG\_PRS\n") */ - Return(IRQP) + Return (IRQP) } /* Method(_SB.INTG._CRS) */

Method(_CRS ,0) { /* DBGO("\_SB\LNKG\_CRS\n") */ CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRG, IRQN) - Return(IRQB) + IRQN = 1 << PIRG + Return (IRQB) } /* Method(_SB.INTG._CRS) */

Method(_SRS, 1) { @@ -452,9 +452,9 @@ /* Use lowest available IRQ */ FindSetRightBit(IRQM, Local0) if (Local0) { - Decrement(Local0) + Local0-- } - Store(Local0, PIRG) + PIRG = Local0 } /* End Method(_SB.INTG._SRS) */ } /* End Device(INTG) */

@@ -464,27 +464,27 @@

Method(_STA, 0) { if (PIRH) { - Return(0x0B) /* sata is invisible */ + Return (0x0b) /* sata is invisible */ } else { - Return(0x09) /* sata is disabled */ + Return (0x09) /* sata is disabled */ } } /* End Method(_SB.INTH._STA) */

Method(_DIS ,0) { /* DBGO("\_SB\LNKH\_DIS\n") */ - Store(0, PIRH) + PIRH = 0 } /* End Method(_SB.INTH._DIS) */

Method(_PRS ,0) { /* DBGO("\_SB\LNKH\_PRS\n") */ - Return(IRQP) + Return (IRQP) } /* Method(_SB.INTH._CRS) */

Method(_CRS ,0) { /* DBGO("\_SB\LNKH\_CRS\n") */ CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRH, IRQN) - Return(IRQB) + IRQN = 1 << PIRH + Return (IRQB) } /* Method(_SB.INTH._CRS) */

Method(_SRS, 1) { @@ -494,9 +494,9 @@ /* Use lowest available IRQ */ FindSetRightBit(IRQM, Local0) if (Local0) { - Decrement(Local0) + Local0-- } - Store(Local0, PIRH) + PIRH = Local0 } /* End Method(_SB.INTH._SRS) */ } /* End Device(INTH) */

diff --git a/src/southbridge/amd/cimx/sb800/acpi/smbus.asl b/src/southbridge/amd/cimx/sb800/acpi/smbus.asl index a676893..b81c5b1 100644 --- a/src/southbridge/amd/cimx/sb800/acpi/smbus.asl +++ b/src/southbridge/amd/cimx/sb800/acpi/smbus.asl @@ -19,37 +19,37 @@ }

Method (WCLR, 0, NotSerialized) { /* clear SMBUS status register */ - Store (0x1E, HSTS) - Store (0xFA, Local0) - While (LAnd (LNotEqual (And (HSTS, 0x1E), Zero), LGreater (Local0, Zero))) { + HSTS = 0x1e + Local0 = 0xfa + While ((HSTS & 0x1e) != 0) && (Local0 > 0)) { Stall (0x64) - Decrement (Local0) + Local0-- }

Return (Local0) }

Method (SWTC, 1, NotSerialized) { - Store (Arg0, Local0) - Store (0x07, Local2) - Store (One, Local1) - While (LEqual (Local1, One)) { - Store (And (HSTS, 0x1E), Local3) - If (LNotEqual (Local3, Zero)) { /* read sucess */ - If (LEqual (Local3, 0x02)) { - Store (Zero, Local2) + Local0 = Arg0 + Local2 = 0x07 + Local1 = 1 + While (Local1 == 1) { + Local3 = HSTS & 0x1e + If (Local3 != 0) { /* read success */ + If (Local3 != 0x02) { + Local2 = 0 }

- Store (0x1F, HSTS) - Store (Or (ShiftLeft (Arg1, One), One), HADD) - Store (Arg2, HCMD) - If (LEqual (Arg0, 0x07)) { - Store (0x48, HCNT) /* read byte */ + HSTS = 0x1f + HADD = (Arg1 << 1) | 1 + HCMD = Arg2 + If (Arg0 == 0x07) { + HCNT = 0x48 /* read byte */ }

Release (SBX0)

-- To view, visit https://review.coreboot.org/c/coreboot/+/45875 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6fd7056d8053f0097b5c9de6b4e2e6db38910a2e Gerrit-Change-Number: 45875 Gerrit-PatchSet: 6 Gerrit-Owner: HAOUAS Elyes ehaouas@noos.fr Gerrit-Reviewer: Angel Pons th3fanbus@gmail.com Gerrit-Reviewer: Kyösti Mälkki kyosti.malkki@gmail.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-MessageType: merged

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Angel Pons (Code Review)
HAOUAS Elyes (Code Review)
Kyösti Mälkki (Code Review)