Change in coreboot[master]: src/cpu/amd: Don't hide pointers behind typedefs

[Elyes HAOUAS (Code Review)]

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/23653

Change subject: src/cpu/amd: Don't hide pointers behind typedefs
......................................................................

src/cpu/amd: Don't hide pointers behind typedefs

See Change 7146

Change-Id: I4b930a191130941c8349861cdd803a5be4219274
Signed-off-by: Elyes HAOUAS 
---
M src/cpu/amd/agesa/family12/model_12_init.c
M src/cpu/amd/agesa/family14/model_14_init.c
M src/cpu/amd/agesa/family15tn/model_15_init.c
M src/cpu/amd/agesa/family16kb/model_16_init.c
M src/cpu/amd/dualcore/amd_sibling.c
M src/cpu/amd/family_10h-family_15h/model_10xxx_init.c
M src/cpu/amd/family_10h-family_15h/processor_name.c
M src/cpu/amd/family_10h-family_15h/ram_calc.c
M src/cpu/amd/geode_lx/geode_lx_init.c
M src/cpu/amd/model_fxx/model_fxx_init.c
M src/cpu/amd/pi/00630F01/model_15_init.c
M src/cpu/amd/pi/00660F01/model_15_init.c
M src/cpu/amd/pi/00730F01/model_16_init.c
13 files changed, 20 insertions(+), 19 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/23653/1

diff --git a/src/cpu/amd/agesa/family12/model_12_init.c b/src/cpu/amd/agesa/family12/model_12_init.c
index 1d414a2..f96ad9e 100644
--- a/src/cpu/amd/agesa/family12/model_12_init.c
+++ b/src/cpu/amd/agesa/family12/model_12_init.c
@@ -31,7 +31,7 @@

#define MCI_STATUS 0x401

-static void model_12_init(device_t dev)
+static void model_12_init(struct device *dev)
 {
    printk(BIOS_DEBUG, "Model 12 Init.\n");

diff --git a/src/cpu/amd/agesa/family14/model_14_init.c b/src/cpu/amd/agesa/family14/model_14_init.c
index a03516d..7fce24f 100644
--- a/src/cpu/amd/agesa/family14/model_14_init.c
+++ b/src/cpu/amd/agesa/family14/model_14_init.c
@@ -32,7 +32,7 @@

#define MCI_STATUS 0x401

-static void model_14_init(device_t dev)
+static void model_14_init(struct device *dev)
 {
    u8 i;
    msr_t msr;
diff --git a/src/cpu/amd/agesa/family15tn/model_15_init.c b/src/cpu/amd/agesa/family15tn/model_15_init.c
index e0bff4f..433a331 100644
--- a/src/cpu/amd/agesa/family15tn/model_15_init.c
+++ b/src/cpu/amd/agesa/family15tn/model_15_init.c
@@ -31,7 +31,7 @@
 #include <arch/acpi.h>
 #include <northbridge/amd/agesa/agesa_helper.h>

-static void model_15_init(device_t dev)
+static void model_15_init(struct device *dev)
 {
    printk(BIOS_DEBUG, "Model 15 Init.\n");

diff --git a/src/cpu/amd/agesa/family16kb/model_16_init.c b/src/cpu/amd/agesa/family16kb/model_16_init.c
index d49216a..5c8684b 100644
--- a/src/cpu/amd/agesa/family16kb/model_16_init.c
+++ b/src/cpu/amd/agesa/family16kb/model_16_init.c
@@ -30,7 +30,7 @@
 #include <arch/acpi.h>
 #include <northbridge/amd/agesa/agesa_helper.h>

-static void model_16_init(device_t dev)
+static void model_16_init(struct device *dev)
 {
    printk(BIOS_DEBUG, "Model 16 Init.\n");

diff --git a/src/cpu/amd/dualcore/amd_sibling.c b/src/cpu/amd/dualcore/amd_sibling.c
index 693ceb8..f45da6a 100644
--- a/src/cpu/amd/dualcore/amd_sibling.c
+++ b/src/cpu/amd/dualcore/amd_sibling.c
@@ -32,7 +32,7 @@

static int get_max_siblings(int nodes)
 {
-	device_t dev;
+	strcut device *dev;
    int nodeid;
    int siblings=0;

@@ -51,7 +51,7 @@

static void enable_apic_ext_id(int nodes)
 {
-	device_t dev;
+	struct device *dev;
    int nodeid;

//enable APIC_EXIT_ID all the nodes
@@ -67,7 +67,7 @@

unsigned get_apicid_base(unsigned ioapic_num)
 {
-	device_t dev;
+	struct device *dev;
    int nodes;
    unsigned apicid_base;
    int siblings;
diff --git a/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c b/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c
index f73ce03..0b7ddc6 100644
--- a/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c
+++ b/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c
@@ -59,7 +59,7 @@

static volatile uint8_t fam15h_startup_flags[MAX_NODES_SUPPORTED][MAX_CORES_SUPPORTED] = {{ 0 }};

-static void model_10xxx_init(device_t dev)
+static void model_10xxx_init(struct device *dev)
 {
    u8 i;
    msr_t msr;
diff --git a/src/cpu/amd/family_10h-family_15h/processor_name.c b/src/cpu/amd/family_10h-family_15h/processor_name.c
index bda8409..857ea02 100644
--- a/src/cpu/amd/family_10h-family_15h/processor_name.c
+++ b/src/cpu/amd/family_10h-family_15h/processor_name.c
@@ -236,7 +236,8 @@
    if (fam15h) {
    	/* Family 15h or later */
    	uint32_t dword;
-		device_t cpu_fn5_dev = dev_find_slot(0, PCI_DEVFN(0x18, 5));
+		struct device *cpu_fn5_dev
+		cpu_fn5_dev = dev_find_slot(0, PCI_DEVFN(0x18, 5));
    	pci_write_config32(cpu_fn5_dev, 0x194, 0);
    	dword = pci_read_config32(cpu_fn5_dev, 0x198);
    	if (dword == 0) {
diff --git a/src/cpu/amd/family_10h-family_15h/ram_calc.c b/src/cpu/amd/family_10h-family_15h/ram_calc.c
index 62b7da3..16caad4 100644
--- a/src/cpu/amd/family_10h-family_15h/ram_calc.c
+++ b/src/cpu/amd/family_10h-family_15h/ram_calc.c
@@ -62,8 +62,8 @@
 uint64_t get_cc6_memory_size()
 {
    uint8_t enable_cc6;
-
    uint64_t cc6_size = 0;
+	struct device *dct_dev;

if (is_fam15h()) {
    	enable_cc6 = 0;
@@ -72,7 +72,7 @@
    	if (pci_read_config32(PCI_DEV(0, 0x18, 2), 0x118) & (0x1 << 18))
    		enable_cc6 = 1;
 #else
-		device_t dct_dev = dev_find_slot(0, PCI_DEVFN(0x18, 2));
+		dct_dev = dev_find_slot(0, PCI_DEVFN(0x18, 2));
    	if (pci_read_config32(dct_dev, 0x118) & (0x1 << 18))
    		enable_cc6 = 1;
 #endif
diff --git a/src/cpu/amd/geode_lx/geode_lx_init.c b/src/cpu/amd/geode_lx/geode_lx_init.c
index 8c0cef3..e620131 100644
--- a/src/cpu/amd/geode_lx/geode_lx_init.c
+++ b/src/cpu/amd/geode_lx/geode_lx_init.c
@@ -33,7 +33,7 @@
    		  ".byte 0x0f, 0x38\n" "pop %ax\n");
 }

-static void geode_lx_init(device_t dev)
+static void geode_lx_init(struct device *dev)
 {
    printk(BIOS_DEBUG, "geode_lx_init\n");

diff --git a/src/cpu/amd/model_fxx/model_fxx_init.c b/src/cpu/amd/model_fxx/model_fxx_init.c
index f5a6773..21e59de 100644
--- a/src/cpu/amd/model_fxx/model_fxx_init.c
+++ b/src/cpu/amd/model_fxx/model_fxx_init.c
@@ -65,7 +65,7 @@
    	return !is_cpu_pre_e0();
    }
    // d0 will be treated as e0 with this methods, but the d0 nb_cfg_54 always 0
-	device_t dev;
+	struct device *dev;
    dev = dev_find_slot(0, PCI_DEVFN(0x18 + nodeid, 2));
    if (!dev)
    	return 0;
@@ -85,7 +85,7 @@
 int is_cpu_f0_in_bsp(int nodeid)
 {
    uint32_t dword;
-	device_t dev;
+	strcut device *dev;

if (!IS_ENABLED(CONFIG_K8_REV_F_SUPPORT))
    	return 0;
@@ -243,7 +243,7 @@
    unsigned long basek;
    struct mtrr_state mtrr_state;

-	device_t f1_dev, f2_dev, f3_dev;
+	struct device *f1_dev, *f2_dev, *f3_dev;
    int enable_scrubbing;
    uint32_t dcl;

@@ -463,7 +463,7 @@
    wrmsr(HWCR_MSR, msr);
 }

-static void model_fxx_init(device_t dev)
+static void model_fxx_init(struct device *dev)
 {
    unsigned long i;
    msr_t msr;
diff --git a/src/cpu/amd/pi/00630F01/model_15_init.c b/src/cpu/amd/pi/00630F01/model_15_init.c
index 5299dca..6c3e594 100644
--- a/src/cpu/amd/pi/00630F01/model_15_init.c
+++ b/src/cpu/amd/pi/00630F01/model_15_init.c
@@ -31,7 +31,7 @@
 #include <cpu/amd/amdfam15.h>
 #include <arch/acpi.h>

-static void model_15_init(device_t dev)
+static void model_15_init(struct device *dev)
 {
    printk(BIOS_DEBUG, "Model 15 Init.\n");

diff --git a/src/cpu/amd/pi/00660F01/model_15_init.c b/src/cpu/amd/pi/00660F01/model_15_init.c
index abe20c3..8a8a0a7 100644
--- a/src/cpu/amd/pi/00660F01/model_15_init.c
+++ b/src/cpu/amd/pi/00660F01/model_15_init.c
@@ -47,7 +47,7 @@
    LibAmdMsrRead(0xC00110A2, &Tmp64, NULL);
 }

-static void model_15_init(device_t dev)
+static void model_15_init(struct device *dev)
 {
    printk(BIOS_DEBUG, "Model 15 Init.\n");

diff --git a/src/cpu/amd/pi/00730F01/model_16_init.c b/src/cpu/amd/pi/00730F01/model_16_init.c
index e0eca94..25cb5dc 100644
--- a/src/cpu/amd/pi/00730F01/model_16_init.c
+++ b/src/cpu/amd/pi/00730F01/model_16_init.c
@@ -30,7 +30,7 @@
 #include <cpu/amd/amdfam16.h>
 #include <arch/acpi.h>

-static void model_16_init(device_t dev)
+static void model_16_init(struct device *dev)
 {
    printk(BIOS_DEBUG, "Model 16 Init.\n");