Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32326
Change subject: kohaku: mb/hatch/gpio: Scrub Kohaku GPIOs. ......................................................................
kohaku: mb/hatch/gpio: Scrub Kohaku GPIOs.
BUG=b:129707481 BRANCH=none TEST=Compiles.
Change-Id: Ie5c83a0538d367ea11e9499f21cea41891d7a78e Signed-off-by: Tim Wawrzynczak twawrzynczak@chromium.org --- M src/mainboard/google/hatch/variants/baseboard/gpio.c A src/mainboard/google/hatch/variants/kohaku/gpio.c 2 files changed, 95 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/32326/1
diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c index 0391dfe..784dd6c 100644 --- a/src/mainboard/google/hatch/variants/baseboard/gpio.c +++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c @@ -232,7 +232,7 @@
/* E0 : GPP_E0 ==> NC */ PAD_NC(GPP_E0, NONE), - /* E1 : SATAPCIE1 */ + /* E1 : M2_SSD_PEDET */ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), /* E2 : GPP_E2 ==> NC */ PAD_NC(GPP_E2, NONE), diff --git a/src/mainboard/google/hatch/variants/kohaku/gpio.c b/src/mainboard/google/hatch/variants/kohaku/gpio.c new file mode 100644 index 0000000..c7d7213 --- /dev/null +++ b/src/mainboard/google/hatch/variants/kohaku/gpio.c @@ -0,0 +1,94 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <commonlib/helpers.h> + +static const struct pad_config gpio_table[] = { + /* RCIN# ==> NC */ + PAD_NC(GPP_A0, NONE), + /* SERIRQ ==> NC */ + PAD_NC(GPP_A6, NONE), + /* PEN_RESET_ODL */ + PAD_CFG_GPO(GPP_A10, 0, DEEP), + /* PIRQA# ==> NC */ + PAD_NC(GPP_A17, NONE), + /* ISH_GP0 ==> NC */ + PAD_NC(GPP_A18, NONE), + /* ISH_GP1 ==> NC */ + PAD_NC(GPP_A19, NONE), + /* ISH_GP2 ==> NC */ + PAD_NC(GPP_A20, NONE), + /* ISH_GP4 ==> NC */ + PAD_NC(GPP_A22, NONE), + /* SRCCLKREQ3#: NC */ + PAD_NC(GPP_B8, NONE), + /* SMBDATA: NC */ + PAD_NC(GPP_C1, NONE), + /* + * Hoping that GPP_A8 can be used for both interrupt (SCI) and wake + * (GPIO). Keeping as GPI for now, but with the option to change later. + */ + PAD_CFG_GPI_SCI(GPP_C12, NONE, DEEP, EDGE_SINGLE, INVERT), + /* EN_PP3300_TSP_DIG_DX */ + PAD_CFG_GPO(GPP_C15, 0, DEEP), + /* UART2_CTS# ==> NC */ + PAD_NC(GPP_C23, NONE), + /* GPP_E23 ==> NC */ + PAD_NC(GPP_E23, NONE), + /* GPP_F1 ==> NC */ + PAD_NC(GPP_F1, NONE), + /* GPP_G0 ==> NC */ + PAD_NC(GPP_G0, NONE), + /* GPP_G1 ==> NC */ + PAD_NC(GPP_G1, NONE), + /* GPP_G2 ==> NC */ + PAD_NC(GPP_G2, NONE), + /* GPP_G3 ==> NC */ + PAD_NC(GPP_G3, NONE), + /* GPP_G4 ==> NC */ + PAD_NC(GPP_G4, NONE), + /* GPP_G5 ==> NC */ + PAD_NC(GPP_G5, NONE), + /* GPP_G6 ==> NC */ + PAD_NC(GPP_G6, NONE), +}; + +const struct pad_config *variant_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +/* + * GPIO settings before entering S5 + */ +static const struct pad_config s5_sleep_gpio_table[] = { + PAD_CFG_GPO(GPP_A12, 1, DEEP), /* FPMCU_RST_ODL */ +}; + +const struct pad_config *sleep_gpio_table(u8 slp_typ, size_t *num) +{ + if (slp_typ == ACPI_S5) { + *num = ARRAY_SIZE(s5_sleep_gpio_table); + return s5_sleep_gpio_table; + } + + *num = ARRAY_SIZE(default_sleep_gpio_table); + return default_sleep_gpio_table; +} +
Hello Paul Fagerburg, Shelley Chen, build bot (Jenkins), Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32326
to look at the new patch set (#2).
Change subject: kohaku: mb/hatch/gpio: Scrub Kohaku GPIOs. ......................................................................
kohaku: mb/hatch/gpio: Scrub Kohaku GPIOs.
BUG=b:129707481 BRANCH=none TEST=Compiles.
Change-Id: Ie5c83a0538d367ea11e9499f21cea41891d7a78e Signed-off-by: Tim Wawrzynczak twawrzynczak@chromium.org --- M src/mainboard/google/hatch/variants/baseboard/gpio.c A src/mainboard/google/hatch/variants/kohaku/gpio.c 2 files changed, 94 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/32326/2
Paul Fagerburg has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32326 )
Change subject: kohaku: mb/hatch/gpio: Scrub Kohaku GPIOs. ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/#/c/32326/2/src/mainboard/google/hatch/variants/... File src/mainboard/google/hatch/variants/kohaku/gpio.c:
https://review.coreboot.org/#/c/32326/2/src/mainboard/google/hatch/variants/... PS2, Line 46: PAD_CFG_GPI_SCI(GPP_C12, NONE, DEEP, EDGE_SINGLE, INVERT), The comment above does not agree with the code
Hello Paul Fagerburg, Shelley Chen, build bot (Jenkins), Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32326
to look at the new patch set (#3).
Change subject: kohaku: mb/hatch/gpio: Scrub Kohaku GPIOs. ......................................................................
kohaku: mb/hatch/gpio: Scrub Kohaku GPIOs.
BUG=b:129707481 BRANCH=none TEST=Compiles.
Change-Id: Ie5c83a0538d367ea11e9499f21cea41891d7a78e Signed-off-by: Tim Wawrzynczak twawrzynczak@chromium.org --- M src/mainboard/google/hatch/variants/baseboard/gpio.c A src/mainboard/google/hatch/variants/kohaku/gpio.c 2 files changed, 95 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/32326/3
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32326 )
Change subject: kohaku: mb/hatch/gpio: Scrub Kohaku GPIOs. ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/#/c/32326/2/src/mainboard/google/hatch/variants/... File src/mainboard/google/hatch/variants/kohaku/gpio.c:
https://review.coreboot.org/#/c/32326/2/src/mainboard/google/hatch/variants/... PS2, Line 46: PAD_CFG_GPI_SCI(GPP_C12, NONE, DEEP, EDGE_SINGLE, INVERT),
The comment above does not agree with the code
Done
Paul Fagerburg has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32326 )
Change subject: kohaku: mb/hatch/gpio: Scrub Kohaku GPIOs. ......................................................................
Patch Set 3: Code-Review+1
LGTM
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32326 )
Change subject: kohaku: mb/hatch/gpio: Scrub Kohaku GPIOs. ......................................................................
Patch Set 3:
(4 comments)
https://review.coreboot.org/#/c/32326/3/src/mainboard/google/hatch/variants/... File src/mainboard/google/hatch/variants/kohaku/gpio.c:
PS3: This file needs to be added to Makefile.inc for kohaku
https://review.coreboot.org/#/c/32326/3/src/mainboard/google/hatch/variants/... PS3, Line 21: gpio_table From the implementation, it looks like you are intending to treat this as an override table? If yes, then this code needs to be updated to take care of that: https://review.coreboot.org/cgit/coreboot.git/tree/src/mainboard/google/hatc...
See https://review.coreboot.org/cgit/coreboot.git/tree/src/mainboard/google/octo... as an example.
With the current implementation, kohaku will end up configuring only the GPIOs in this table.
https://review.coreboot.org/#/c/32326/3/src/mainboard/google/hatch/variants/... PS3, Line 87: ACPI_S5 There is no need to distinguish sleep type if there is only one sleep gpio table.
https://review.coreboot.org/#/c/32326/3/src/mainboard/google/hatch/variants/... PS3, Line 92: default_sleep_gpio_table Where is this defined?
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32326 )
Change subject: kohaku: mb/hatch/gpio: Scrub Kohaku GPIOs. ......................................................................
Patch Set 3:
(4 comments)
https://review.coreboot.org/#/c/32326/3/src/mainboard/google/hatch/variants/... File src/mainboard/google/hatch/variants/kohaku/gpio.c:
PS3:
This file needs to be added to Makefile. […]
Done
https://review.coreboot.org/#/c/32326/3/src/mainboard/google/hatch/variants/... PS3, Line 21: gpio_table
From the implementation, it looks like you are intending to treat this as an override table? If yes, […]
I see. Based on octopus, I had thought that providing the override table would just work. I think the base + override method is the way to go, so I will update to use that.
https://review.coreboot.org/#/c/32326/3/src/mainboard/google/hatch/variants/... PS3, Line 87: ACPI_S5
There is no need to distinguish sleep type if there is only one sleep gpio table.
Done
https://review.coreboot.org/#/c/32326/3/src/mainboard/google/hatch/variants/... PS3, Line 92: default_sleep_gpio_table
Where is this defined?
Oops. Not here.
Hello Paul Fagerburg, Shelley Chen, build bot (Jenkins), Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32326
to look at the new patch set (#4).
Change subject: kohaku: mb/hatch/gpio: Scrub Kohaku GPIOs. ......................................................................
kohaku: mb/hatch/gpio: Scrub Kohaku GPIOs.
Ensure Kohaku GPIO pins are configured correctly w/r/t Hatch. Implement the base/override model for GPIOs (regular and early). The 'hatch' baseboard contains the base GPIOs, and variants can override individual pads.
BUG=b:129707481 BRANCH=none TEST=Compiles for all variants.
Change-Id: Ie5c83a0538d367ea11e9499f21cea41891d7a78e Signed-off-by: Tim Wawrzynczak twawrzynczak@chromium.org --- M src/mainboard/google/hatch/bootblock.c M src/mainboard/google/hatch/ramstage.c M src/mainboard/google/hatch/variants/baseboard/gpio.c M src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/hatch/variants/hatch_whl/Makefile.inc A src/mainboard/google/hatch/variants/hatch_whl/gpio.c M src/mainboard/google/hatch/variants/kohaku/Makefile.inc A src/mainboard/google/hatch/variants/kohaku/gpio.c M src/soc/intel/cannonlake/chip.c 9 files changed, 193 insertions(+), 49 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/32326/4
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32326 )
Change subject: kohaku: mb/hatch/gpio: Scrub Kohaku GPIOs. ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/#/c/32326/4/src/mainboard/google/hatch/variants/... File src/mainboard/google/hatch/variants/baseboard/gpio.c:
https://review.coreboot.org/#/c/32326/4/src/mainboard/google/hatch/variants/... PS4, Line 407: const struct pad_config * base_gpio_table(size_t *num) "foo * bar" should be "foo *bar"
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32326 )
Change subject: kohaku: mb/hatch/gpio: Scrub Kohaku GPIOs. ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/#/c/32326/4/src/soc/intel/cannonlake/chip.c File src/soc/intel/cannonlake/chip.c:
https://review.coreboot.org/#/c/32326/4/src/soc/intel/cannonlake/chip.c@a148 PS4, Line 148: Typically, we push separate CLs for mainboard and SoC changes. So, this CL will have to be split into two different changes.
BTW, this function is still being used by sarien/arcada. +Duncan to make sure things look good there as well w.r.t. GPIO configuration.
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32326 )
Change subject: kohaku: mb/hatch/gpio: Scrub Kohaku GPIOs. ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/#/c/32326/4/src/mainboard/google/hatch/variants/... File src/mainboard/google/hatch/variants/hatch_whl/gpio.c:
PS4: This file is not required, since it will end up using the weak functions.
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32326 )
Change subject: kohaku: mb/hatch/gpio: Scrub Kohaku GPIOs. ......................................................................
Patch Set 4:
(2 comments)
https://review.coreboot.org/#/c/32326/4/src/mainboard/google/hatch/variants/... File src/mainboard/google/hatch/variants/hatch_whl/gpio.c:
PS4:
This file is not required, since it will end up using the weak functions.
Ah yes, I guess it isn't needed at all. Good catch.
https://review.coreboot.org/#/c/32326/4/src/soc/intel/cannonlake/chip.c File src/soc/intel/cannonlake/chip.c:
https://review.coreboot.org/#/c/32326/4/src/soc/intel/cannonlake/chip.c@a148 PS4, Line 148:
Typically, we push separate CLs for mainboard and SoC changes. […]
No problem, I'll split it up and add Duncan.
Hello Patrick Rudolph, Paul Fagerburg, Duncan Laurie, Shelley Chen, build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32326
to look at the new patch set (#5).
Change subject: kohaku: mb/hatch/gpio: Scrub Kohaku GPIOs. ......................................................................
kohaku: mb/hatch/gpio: Scrub Kohaku GPIOs.
Ensure Kohaku GPIO pins are configured correctly w/r/t Hatch. Implement the base/override model for GPIOs (regular and early). The 'hatch' baseboard contains the base GPIOs, and variants can override individual pads.
BUG=b:129707481 BRANCH=none TEST=Compiles for all variants.
Change-Id: Ie5c83a0538d367ea11e9499f21cea41891d7a78e Signed-off-by: Tim Wawrzynczak twawrzynczak@chromium.org --- M src/mainboard/google/hatch/bootblock.c M src/mainboard/google/hatch/ramstage.c M src/mainboard/google/hatch/variants/baseboard/gpio.c M src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/hatch/variants/kohaku/Makefile.inc A src/mainboard/google/hatch/variants/kohaku/gpio.c 6 files changed, 154 insertions(+), 19 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/32326/5
Paul Fagerburg has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32326 )
Change subject: kohaku: mb/hatch/gpio: Scrub Kohaku GPIOs. ......................................................................
Patch Set 5: Code-Review+1
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32326 )
Change subject: kohaku: mb/hatch/gpio: Scrub Kohaku GPIOs. ......................................................................
Patch Set 5: Code-Review+2
Does this change still boot fine on hatch whl?
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32326 )
Change subject: kohaku: mb/hatch/gpio: Scrub Kohaku GPIOs. ......................................................................
Patch Set 5:
Patch Set 5: Code-Review+2
Does this change still boot fine on hatch whl?
Confirmed.
Furquan Shaikh has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/32326 )
Change subject: kohaku: mb/hatch/gpio: Scrub Kohaku GPIOs. ......................................................................
kohaku: mb/hatch/gpio: Scrub Kohaku GPIOs.
Ensure Kohaku GPIO pins are configured correctly w/r/t Hatch. Implement the base/override model for GPIOs (regular and early). The 'hatch' baseboard contains the base GPIOs, and variants can override individual pads.
BUG=b:129707481 BRANCH=none TEST=Compiles for all variants.
Change-Id: Ie5c83a0538d367ea11e9499f21cea41891d7a78e Signed-off-by: Tim Wawrzynczak twawrzynczak@chromium.org Reviewed-on: https://review.coreboot.org/c/coreboot/+/32326 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Paul Fagerburg pfagerburg@chromium.org Reviewed-by: Furquan Shaikh furquan@google.com --- M src/mainboard/google/hatch/bootblock.c M src/mainboard/google/hatch/ramstage.c M src/mainboard/google/hatch/variants/baseboard/gpio.c M src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/hatch/variants/kohaku/Makefile.inc A src/mainboard/google/hatch/variants/kohaku/gpio.c 6 files changed, 154 insertions(+), 19 deletions(-)
Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Paul Fagerburg: Looks good to me, but someone else must approve
diff --git a/src/mainboard/google/hatch/bootblock.c b/src/mainboard/google/hatch/bootblock.c index 9cde37a..9534af1 100644 --- a/src/mainboard/google/hatch/bootblock.c +++ b/src/mainboard/google/hatch/bootblock.c @@ -19,11 +19,18 @@
static void early_config_gpio(void) { - const struct pad_config *early_gpio_table; - size_t num_gpios = 0; + const struct pad_config *base_early_table; + const struct pad_config *override_early_table; + size_t base_gpios; + size_t override_gpios;
- early_gpio_table = variant_early_gpio_table(&num_gpios); - gpio_configure_pads(early_gpio_table, num_gpios); + base_early_table = base_early_gpio_table(&base_gpios); + override_early_table = override_early_gpio_table(&override_gpios); + + gpio_configure_pads_with_override(base_early_table, + base_gpios, + override_early_table, + override_gpios); }
void bootblock_mainboard_init(void) diff --git a/src/mainboard/google/hatch/ramstage.c b/src/mainboard/google/hatch/ramstage.c index 5824e66..3436007 100644 --- a/src/mainboard/google/hatch/ramstage.c +++ b/src/mainboard/google/hatch/ramstage.c @@ -23,11 +23,18 @@
void mainboard_silicon_init_params(FSP_S_CONFIG *params) { - const struct pad_config *gpio_table; - size_t num_gpios; + const struct pad_config *base_table; + const struct pad_config *override_table; + size_t base_gpios; + size_t override_gpios;
- gpio_table = variant_gpio_table(&num_gpios); - cnl_configure_pads(gpio_table, num_gpios); + base_table = base_gpio_table(&base_gpios); + override_table = override_gpio_table(&override_gpios); + + gpio_configure_pads_with_override(base_table, + base_gpios, + override_table, + override_gpios); }
static void mainboard_enable(struct device *dev) diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c index eaa8dd3..7e82b9b 100644 --- a/src/mainboard/google/hatch/variants/baseboard/gpio.c +++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c @@ -232,7 +232,7 @@
/* E0 : GPP_E0 ==> NC */ PAD_NC(GPP_E0, NONE), - /* E1 : SATAPCIE1 */ + /* E1 : M2_SSD_PEDET */ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), /* E2 : GPP_E2 ==> NC */ PAD_NC(GPP_E2, NONE), @@ -344,7 +344,6 @@ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1), /* G7 : SD_WP => NC */ PAD_NC(GPP_G7, DN_20K), - /* * H0 : HP_INT_L * TODO Configure it back to invert mode, when @@ -405,7 +404,7 @@ PAD_CFG_GPI_GPIO_DRIVER(vSD3_CD_B, NONE, DEEP), };
-const struct pad_config *__weak variant_gpio_table(size_t *num) +const struct pad_config *base_gpio_table(size_t *num) { *num = ARRAY_SIZE(gpio_table); return gpio_table; @@ -429,8 +428,8 @@ PAD_CFG_GPO(GPP_A18, 0, DEEP), /* EN_PP3300_WWAN */ };
-const struct pad_config * __weak -variant_sleep_gpio_table(u8 slp_typ, size_t *num) +const struct pad_config * __weak variant_sleep_gpio_table( + u8 slp_typ, size_t *num) { if (slp_typ == ACPI_S5) { *num = ARRAY_SIZE(s5_sleep_gpio_table); @@ -470,10 +469,9 @@ PAD_CFG_GPI(GPP_F21, NONE, PLTRST), /* F22 : PCH_MEM_STRAP3 */ PAD_CFG_GPI(GPP_F22, NONE, PLTRST), - };
-const struct pad_config *__weak variant_early_gpio_table(size_t *num) +const struct pad_config *base_early_gpio_table(size_t *num) { *num = ARRAY_SIZE(early_gpio_table); return early_gpio_table; @@ -489,3 +487,16 @@ *num = ARRAY_SIZE(cros_gpios); return cros_gpios; } + +/* Weak implementation of overrides */ +const struct pad_config *__weak override_gpio_table(size_t *num) +{ + *num = 0; + return NULL; +} + +const struct pad_config *__weak override_early_gpio_table(size_t *num) +{ + *num = 0; + return NULL; +} diff --git a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h index fd39c45..d41ad53 100644 --- a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h @@ -21,10 +21,15 @@ #include <stdint.h> #include <vendorcode/google/chromeos/chromeos.h>
-/* The next set of functions return the gpio table and fill in the number of - * entries for each table. */ -const struct pad_config *variant_gpio_table(size_t *num); -const struct pad_config *variant_early_gpio_table(size_t *num); +/* + * The next set of functions return the gpio table and fill in the number of + * entries for each table. The "base" GPIOs live in the "hatch" variant, and + * the overrides live with the specific board (kohaku, kled, etc.). +*/ +const struct pad_config *base_gpio_table(size_t *num); +const struct pad_config *base_early_gpio_table(size_t *num); +const struct pad_config *override_gpio_table(size_t *num); +const struct pad_config *override_early_gpio_table(size_t *num);
/* Return memory SKU for the board. */ int variant_memory_sku(void); diff --git a/src/mainboard/google/hatch/variants/kohaku/Makefile.inc b/src/mainboard/google/hatch/variants/kohaku/Makefile.inc index cf6ee5a..2f590bf 100644 --- a/src/mainboard/google/hatch/variants/kohaku/Makefile.inc +++ b/src/mainboard/google/hatch/variants/kohaku/Makefile.inc @@ -18,3 +18,6 @@ SPD_SOURCES += 8G_2666 # 0b011 SPD_SOURCES += 16G_2400 # 0b100 SPD_SOURCES += 16G_2666 # 0b101 + +bootblock-y += gpio.c +ramstage-y += gpio.c diff --git a/src/mainboard/google/hatch/variants/kohaku/gpio.c b/src/mainboard/google/hatch/variants/kohaku/gpio.c new file mode 100644 index 0000000..88c1d7b --- /dev/null +++ b/src/mainboard/google/hatch/variants/kohaku/gpio.c @@ -0,0 +1,102 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <commonlib/helpers.h> + +static const struct pad_config gpio_table[] = { + /* A0 : RCIN# ==> NC */ + PAD_NC(GPP_A0, NONE), + /* A6 : SERIRQ ==> NC */ + PAD_NC(GPP_A6, NONE), + /* A10 : PEN_RESET_ODL */ + PAD_CFG_GPO(GPP_A10, 0, DEEP), + /* A17 : PIRQA# ==> NC */ + PAD_NC(GPP_A17, NONE), + /* A18 : ISH_GP0 ==> NC */ + PAD_NC(GPP_A18, NONE), + /* A19 : ISH_GP1 ==> NC */ + PAD_NC(GPP_A19, NONE), + /* A20 : ISH_GP2 ==> NC */ + PAD_NC(GPP_A20, NONE), + /* A22 : ISH_GP4 ==> NC */ + PAD_NC(GPP_A22, NONE), + /* B8 : SRCCLKREQ3#: NC */ + PAD_NC(GPP_B8, NONE), + /* C1 : SMBDATA: NC */ + PAD_NC(GPP_C1, NONE), + /* + * C12 : EMR_GARAGE_INT + * The same signal is routed to both A8 and C12. Currently C12 + * is the interrupt source, and A8 is the wake source. + * Hoping that GPP_A8 can be used for both interrupt (SCI) and wake + * (GPIO). Keeping as GPI for now. + */ + PAD_CFG_GPI_SCI(GPP_C12, NONE, DEEP, EDGE_SINGLE, INVERT), + /* C15 : EN_PP3300_TSP_DIG_DX */ + PAD_CFG_GPO(GPP_C15, 0, DEEP), + /* C23 : UART2_CTS# ==> NC */ + PAD_NC(GPP_C23, NONE), + /* E23 : GPP_E23 ==> NC */ + PAD_NC(GPP_E23, NONE), + /* F1 : GPP_F1 ==> NC */ + PAD_NC(GPP_F1, NONE), + /* G0 : GPP_G0 ==> NC */ + PAD_NC(GPP_G0, NONE), + /* G1 : GPP_G1 ==> NC */ + PAD_NC(GPP_G1, NONE), + /* G2 : GPP_G2 ==> NC */ + PAD_NC(GPP_G2, NONE), + /* G3 : GPP_G3 ==> NC */ + PAD_NC(GPP_G3, NONE), + /* G4 : GPP_G4 ==> NC */ + PAD_NC(GPP_G4, NONE), + /* G5 : GPP_G5 ==> NC */ + PAD_NC(GPP_G5, NONE), + /* G6 : GPP_G6 ==> NC */ + PAD_NC(GPP_G6, NONE), +}; + +const struct pad_config *override_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +/* GPIOs configured before ramstage */ +static const struct pad_config early_gpio_table[] = { + PAD_NC(GPP_C23, NONE), +}; + +const struct pad_config *override_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +/* + * GPIO settings before entering all sleep states + */ +static const struct pad_config sleep_gpio_table[] = { + PAD_CFG_GPO(GPP_A12, 1, DEEP), /* FPMCU_RST_ODL */ +}; + +const struct pad_config *variant_sleep_gpio_table(u8 slp_typ, size_t *num) +{ + *num = ARRAY_SIZE(sleep_gpio_table); + return sleep_gpio_table; +}