Change in coreboot[master]: psp_verstage: add new svc for cezanne

[Kangheui Won (Code Review)]

Kangheui Won has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61368 )

Change subject: psp_verstage: add new svc for cezanne
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Patch Set 4:

(1 comment)

File src/vendorcode/amd/fsp/cezanne/include/bl_uapp/bl_syscall_public.h:

https://review.coreboot.org/c/coreboot/+/61368/comment/38dc0e50_e02cf693 
PS4, Line 145:     NON_CHROME_BOOK_BOOT_MODE                = 0x0,
             :     CHROME_BOOK_BOOT_MODE_UNSIGNED_VERSTAGE  = 0x1,
             :     CHROME_BOOK_BOOT_MODE_PRODUCTION         = 0x2,
             :     CHROME_BOOK_BOOT_MODE_DEVELOPER          = 0x3,
             :     CHROME_BOOK_BOOT_MODE_TYPE_MAX_LIMIT     = 0x4, // used for boundary check
> Please indent with a tab. It’d be great, if you sent a fix-up, as this seems to have slipped review. […]

AMD releases PSP binary to Google with syscall headers. Most of (if not all) contents here are copied from there. And we try to minimize the difference between coreboot version and AMD version, that's the main reason we have few off-format things in here.

I'm not sure what's the policy on src/vendorcode, but if we want proper formatting here it'd better to fix up whole file (e.g. line 35-53). WDYT?