Change in coreboot[master]: [TEST-ONLY / HACK] Mirror payload in RAM before hashing/decompression

[Werner Zeh (Code Review)]

Attention is currently required from: Julius Werner.
Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59767 )

Change subject: [TEST-ONLY / HACK] Mirror payload in RAM before hashing/decompression
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Patch Set 1:

(1 comment)

Patchset:

PS1: 
With this patch I get now much better boot times , so it seems to help somehow:
(load payload was 9,352,958 just without this patch)

39 entries total:

0:1st timestamp                                     36,056
  11:start of bootblock                                46,376 (10,320)
  12:end of bootblock                                  72,085 (25,708)
  13:starting to load romstage                         72,113 (27)
  14:finished loading romstage                         88,561 (16,447)
   1:start of romstage                                 88,587 (26)
 970:loading FSP-M                                     112,200 (23,613)
   2:before RAM initialization                         216,946 (104,745)
 950:calling FspMemoryInit                             223,282 (6,335)
 951:returning from FspMemoryInit                      486,663 (263,380)
   3:after RAM initialization                          494,963 (8,300)
   4:end of romstage                                   513,677 (18,713)
 100:start of postcar                                  524,544 (10,867)
 101:end of postcar                                    524,545 (0)
   8:starting to load ramstage                         524,768 (222)
  15:starting LZMA decompress (ignore for x86)         561,153 (36,385)
  16:finished LZMA decompress (ignore for x86)         576,091 (14,938)
   9:finished loading ramstage                         576,203 (112)
  10:start of ramstage                                 585,969 (9,765)
  17:starting LZ4 decompress (ignore for x86)          634,573 (48,604)
  18:finished LZ4 decompress (ignore for x86)          634,674 (101)
  30:device enumeration                                646,907 (12,232)
 971:loading FSP-S                                     653,502 (6,594)
 954:calling FspSiliconInit                            653,515 (13)
 955:returning from FspSiliconInit                     688,218 (34,702)
  40:device configuration                              729,560 (41,341)
 956:calling FspNotify(AfterPciEnumeration)            734,554 (4,994)
 957:returning from FspNotify(AfterPciEnumeration)     734,810 (255)
  50:device enable                                     734,812 (1)
  60:device initialization                             774,419 (39,607)
  70:device setup done                                 805,197 (30,777)
  75:cbmem post                                        805,206 (8)
  80:write tables                                      808,436 (3,230)
  85:finalize chips                                    817,048 (8,611)
  90:starting to load payload                          818,744 (1,696)
 958:calling FspNotify(ReadyToBoot)                    3,168,059 (2,349,314)
 959:returning from FspNotify(ReadyToBoot)             3,168,720 (661)
 960:calling FspNotify(EndOfFirmware)                  3,168,720 (0)
 961:returning from FspNotify(EndOfFirmware)           3,169,604 (883)
  99:selfboot jump                                     3,170,415 (810)

I still need to understand what happens there exactly though.