[M] Change in coreboot[master]: soc/amd/mendocino: Enhance DPTC_INPUT to support 13 DPTC thermal para...
Attention is currently required from: Jason Glenesk, Raul Rangel, EricKY Cheng, Matt DeVillier, Fred Reitberger, Felix Held.
Tim Van Patten has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68649 )
Change subject: soc/amd/mendocino: Enhance DPTC_INPUT to support 13 DPTC thermal parameters ......................................................................
Patch Set 18:
(2 comments)
File src/soc/amd/mendocino/root_complex.c:
https://review.coreboot.org/c/coreboot/+/68649/comment/768c1fa8_9992db44 PS16, Line 393: #else
Done
Please don't resolve comments that are still open.
This change disables the feature to boot with low/no battery when `FEATURE_DYNAMIC_DPTC` is enabled. That feature needs to remain enabled even when `FEATURE_DYNAMIC_DPTC` is enabled for a device.
The additional DPTC parameters need to be added to all calls, including normal and low/no battery, since those are a part of or override any thermal tuning: 1. Normal mode is table A. 2. Low/No battery is even further throttled than any thermal tuning, to reduce the SOC power draw as much as possible to prevent overwhelming the AC charger.
File src/soc/amd/mendocino/root_complex.c:
https://review.coreboot.org/c/coreboot/+/68649/comment/cef296a5_1334c4ea PS18, Line 269: /* Normal mode DPTC values. */ This is (or at least should be) a duplicate of the default table that's already defined below, and should be removed.
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Tim Van Patten (Code Review)