Hello Nico Huber, Thomas Heijligen,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/39976
to review the following change.
Change subject: [WIP] mb/siemens/field_pg_m6: Add new mainboard ......................................................................
[WIP] mb/siemens/field_pg_m6: Add new mainboard
Change-Id: I1d3508b615ec877edc8db756e9ad38132b37219c Signed-off-by: Thomas Heijligen thomas.heijligen@secunet.com Signed-off-by: Nico Huber nico.huber@secunet.com Signed-off-by: Felix Singer felix.singer@secunet.com --- A src/mainboard/siemens/field_pg_m6/Kconfig A src/mainboard/siemens/field_pg_m6/Kconfig.name A src/mainboard/siemens/field_pg_m6/Makefile.inc A src/mainboard/siemens/field_pg_m6/board_info.txt A src/mainboard/siemens/field_pg_m6/dsdt.asl A src/mainboard/siemens/field_pg_m6/gma-mainboard.ads A src/mainboard/siemens/field_pg_m6/mainboard.c A src/mainboard/siemens/field_pg_m6/romstage.c A src/mainboard/siemens/field_pg_m6/variant.h A src/mainboard/siemens/field_pg_m6/variants/base/Makefile.inc A src/mainboard/siemens/field_pg_m6/variants/base/board_info.txt A src/mainboard/siemens/field_pg_m6/variants/base/data.vbt A src/mainboard/siemens/field_pg_m6/variants/base/devicetree.cb A src/mainboard/siemens/field_pg_m6/variants/base/gpio.c 14 files changed, 438 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/39976/1
diff --git a/src/mainboard/siemens/field_pg_m6/Kconfig b/src/mainboard/siemens/field_pg_m6/Kconfig new file mode 100644 index 0000000..fec610c --- /dev/null +++ b/src/mainboard/siemens/field_pg_m6/Kconfig @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: GPL-2.0-only +# This file is part of the coreboot project. + +if BOARD_SIEMENS_FIELD_PG_M6_BASE + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_32768 + select DRIVERS_I2C_GENERIC + select DRIVERS_I2C_HID + select DRIVERS_UART_8250IO + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select MAINBOARD_HAS_LIBGFXINIT + select MAINBOARD_USES_IFD_GBE_REGION + select SOC_INTEL_CANNONLAKE_PCH_H + select SOC_INTEL_COFFEELAKE + +config MAINBOARD_DIR + string + default "siemens/field_pg_m6" + +config MAINBOARD_FAMILY + string + default "Field PG M6" + +config MAINBOARD_PART_NUMBER + string + default "Field PG M6" + +config VARIANT_DIR + string + default "base" if BOARD_SIEMENS_FIELD_PG_M6_BASE + +config MAX_CPUS + int + default 12 + +config DEVICETREE + string + default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" + +config INTEL_GMA_VBT_FILE + string + default "src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/data.vbt" + +config DIMM_SPD_SIZE + int + default 512 + +config CBFS_SIZE + hex + default 0xb00000 + +endif diff --git a/src/mainboard/siemens/field_pg_m6/Kconfig.name b/src/mainboard/siemens/field_pg_m6/Kconfig.name new file mode 100644 index 0000000..00cba93 --- /dev/null +++ b/src/mainboard/siemens/field_pg_m6/Kconfig.name @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-only +# This file is part of the coreboot project. + +comment "Field PG M6" + +config BOARD_SIEMENS_FIELD_PG_M6_BASE + bool "-> Basic port" diff --git a/src/mainboard/siemens/field_pg_m6/Makefile.inc b/src/mainboard/siemens/field_pg_m6/Makefile.inc new file mode 100644 index 0000000..8c563df --- /dev/null +++ b/src/mainboard/siemens/field_pg_m6/Makefile.inc @@ -0,0 +1,11 @@ +## SPDX-License-Identifier: GPL-2.0-only +## This file is part of the coreboot project. + +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR) + +romstage-y += romstage.c + +ramstage-y += mainboard.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +subdirs-y += variants/$(VARIANT_DIR) diff --git a/src/mainboard/siemens/field_pg_m6/board_info.txt b/src/mainboard/siemens/field_pg_m6/board_info.txt new file mode 100644 index 0000000..cb5b428 --- /dev/null +++ b/src/mainboard/siemens/field_pg_m6/board_info.txt @@ -0,0 +1,5 @@ +Vendor name: Siemens +Category: eval +ROM protocol: SPI +ROM socketed: n +Flashrom support: n diff --git a/src/mainboard/siemens/field_pg_m6/dsdt.asl b/src/mainboard/siemens/field_pg_m6/dsdt.asl new file mode 100644 index 0000000..041fd4f --- /dev/null +++ b/src/mainboard/siemens/field_pg_m6/dsdt.asl @@ -0,0 +1,25 @@ +/* + * SPDX-License-Identifier: GPL-2.0-only + * This file is part of the coreboot project. + */ + +#include <arch/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 // OEM revision +) +{ + #include <soc/intel/cannonlake/acpi/platform.asl> + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> + + Device (_SB.PCI0) { + #include <soc/intel/common/block/acpi/acpi/northbridge.asl> + #include <soc/intel/cannonlake/acpi/southbridge.asl> + } + + #include <southbridge/intel/common/acpi/sleepstates.asl> +} diff --git a/src/mainboard/siemens/field_pg_m6/gma-mainboard.ads b/src/mainboard/siemens/field_pg_m6/gma-mainboard.ads new file mode 100644 index 0000000..82da885 --- /dev/null +++ b/src/mainboard/siemens/field_pg_m6/gma-mainboard.ads @@ -0,0 +1,26 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later +-- This file is part of the coreboot project. + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + -- For a three-pipe setup, bandwidth is shared between the 2nd and + -- the 3rd pipe (if it's not eDP). Thus, probe ports that likely + -- have a high-resolution display attached first, `Internal` last. + + ports : constant Port_List := + (DP2, + DP3, + HDMI1, + HDMI2, + HDMI3, + Analog, + eDP, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/siemens/field_pg_m6/mainboard.c b/src/mainboard/siemens/field_pg_m6/mainboard.c new file mode 100644 index 0000000..508ba22 --- /dev/null +++ b/src/mainboard/siemens/field_pg_m6/mainboard.c @@ -0,0 +1,21 @@ +/* + * SPDX-License-Identifier: GPL-2.0-only + * This file is part of the coreboot project. + */ + +#include <device/device.h> +#include <soc/gpio.h> +#include "variant.h" + +static void mainboard_init(void *chip_info) +{ + const struct pad_config *pads; + size_t num; + + pads = variant_gpio_table(&num); + gpio_configure_pads(pads, num); +} + +struct chip_operations mainboard_ops = { + .init = mainboard_init, +}; diff --git a/src/mainboard/siemens/field_pg_m6/romstage.c b/src/mainboard/siemens/field_pg_m6/romstage.c new file mode 100644 index 0000000..380fc15 --- /dev/null +++ b/src/mainboard/siemens/field_pg_m6/romstage.c @@ -0,0 +1,26 @@ +/* + * SPDX-License-Identifier: GPL-2.0-only + * This file is part of the coreboot project. + */ + +#include <soc/cnl_memcfg_init.h> +#include <soc/romstage.h> +#include <spd_bin.h> + +void mainboard_memory_init_params(FSPM_UPD *memupd) +{ + const struct cnl_mb_cfg cfg = { + .spd = { + [0] = { READ_SMBUS, { 0x50 << 1 }}, + [2] = { READ_SMBUS, { 0x52 << 1 }}, + }, + .rcomp_resistor = { 121, 75, 100 }, + .rcomp_targets = { 50, 25, 20, 20, 26 }, + .dq_pins_interleaved = 1, + .vref_ca_config = 2, + .ect = 0, + }; + cannonlake_memcfg_init(&memupd->FspmConfig, &cfg); + memupd->FspmConfig.EccSupport = 1; + memupd->FspmConfig.UserBd = BOARD_TYPE_MOBILE; +} diff --git a/src/mainboard/siemens/field_pg_m6/variant.h b/src/mainboard/siemens/field_pg_m6/variant.h new file mode 100644 index 0000000..68f9afb --- /dev/null +++ b/src/mainboard/siemens/field_pg_m6/variant.h @@ -0,0 +1,11 @@ +/* + * SPDX-License-Identifier: GPL-2.0-only + * This file is part of the coreboot project. + */ + +#ifndef _VARIANT_H_ +#define _VARIANT_H_ + +const struct pad_config *variant_gpio_table(size_t *num); + +#endif /* _VARIANT_H_ */ diff --git a/src/mainboard/siemens/field_pg_m6/variants/base/Makefile.inc b/src/mainboard/siemens/field_pg_m6/variants/base/Makefile.inc new file mode 100644 index 0000000..fdd7104 --- /dev/null +++ b/src/mainboard/siemens/field_pg_m6/variants/base/Makefile.inc @@ -0,0 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-only +## This file is part of the coreboot project. + +ramstage-y += gpio.c diff --git a/src/mainboard/siemens/field_pg_m6/variants/base/board_info.txt b/src/mainboard/siemens/field_pg_m6/variants/base/board_info.txt new file mode 100644 index 0000000..199a44e --- /dev/null +++ b/src/mainboard/siemens/field_pg_m6/variants/base/board_info.txt @@ -0,0 +1 @@ +Board name: Field PG M6 diff --git a/src/mainboard/siemens/field_pg_m6/variants/base/data.vbt b/src/mainboard/siemens/field_pg_m6/variants/base/data.vbt new file mode 100644 index 0000000..f79a6005 --- /dev/null +++ b/src/mainboard/siemens/field_pg_m6/variants/base/data.vbt Binary files differ diff --git a/src/mainboard/siemens/field_pg_m6/variants/base/devicetree.cb b/src/mainboard/siemens/field_pg_m6/variants/base/devicetree.cb new file mode 100644 index 0000000..8fd83dd --- /dev/null +++ b/src/mainboard/siemens/field_pg_m6/variants/base/devicetree.cb @@ -0,0 +1,114 @@ +# SPDX-License-Identifier: GPL-2.0-only +# This file is part of the coreboot project. + +chip soc/intel/cannonlake + + # TODO + # FSP configuration + register "SaGv" = "SaGv_Enabled" + register "RMT" = "0" + + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC2)" # Type-C? + register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" # single blue + register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # SIMATIC NET CP 5711 + register "usb2_ports[7]" = "USB2_PORT_MID(OC1)" # upper blue + register "usb2_ports[8]" = "USB2_PORT_MID(OC4)" # lower blue + register "usb2_ports[11]" = "USB2_PORT_MID(OC_SKIP)" # STM SC? + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # Type-C? + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # upper blue + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC4)" # lower blue + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Realtek storage? + register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)" # single blue + + register "SataSalpSupport" = "1" + register "SataPortsEnable[0]" = "1" + register "SataPortsEnable[1]" = "1" + register "SataPortsEnable[2]" = "1" + register "SataPortsEnable[3]" = "1" + + register "PchHdaDspEnable" = "0" + register "PchHdaAudioLinkHda" = "1" + + register "PcieRpEnable[0]" = "1" + register "PcieRpEnable[5]" = "1" + register "PcieRpEnable[16]" = "1" + + register "PcieClkSrcUsage[2]" = "0" + register "PcieClkSrcUsage[5]" = "5" + register "PcieClkSrcUsage[7]" = "16" + + register "PcieClkSrcClkReq[2]" = "2" + register "PcieClkSrcClkReq[5]" = "5" + register "PcieClkSrcClkReq[7]" = "7" + + # Enable "Intel Speed Shift Technology" + register "speed_shift_enable" = "1" + + # HECI + register "HeciEnabled" = "1" + + device cpu_cluster 0 on + device lapic 0 on end + end + + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 04.0 off end # SA Thermal device + device pci 12.0 on end # Thermal Subsystem + device pci 12.5 off end # UFS SCS + device pci 12.6 off end # GSPI #2 + device pci 13.0 off end # ISH + device pci 14.0 on end # USB xHCI + device pci 14.1 off end # USB xDCI (OTG) + device pci 14.2 on end # Shared SRAM + device pci 14.5 off end # SDCard + device pci 15.0 off end # I2C #0 + device pci 15.1 off end # I2C #1 + device pci 15.2 off end # I2C #2 + device pci 15.3 off end # I2C #3 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 16.5 off end # Management Engine Interface 4 + device pci 17.0 on end # SATA + device pci 19.0 off end # I2C #4 + device pci 19.2 off end # UART #2 + device pci 1a.0 off end # eMMC + device pci 1c.0 on end # PCI Express Port 1 + device pci 1c.1 off end # PCI Express Port 2 + device pci 1c.2 off end # PCI Express Port 3 + device pci 1c.3 off end # PCI Express Port 4 + device pci 1c.4 off end # PCI Express Port 5 + device pci 1c.5 on end # PCI Express Port 6 + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 off end # PCI Express Port 9 + device pci 1d.1 off end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1d.4 off end # PCI Express Port 13 + device pci 1d.5 off end # PCI Express Port 14 + device pci 1d.6 off end # PCI Express Port 15 + device pci 1d.7 off end # PCI Express Port 16 + device pci 1b.0 on end # PCI Express Port 17 x4 + device pci 1b.4 off end # PCI Express Port 21 + device pci 1b.5 off end # PCI Express Port 22 + device pci 1b.6 off end # PCI Express Port 23 + device pci 1b.7 off end # PCI Express Port 24 + device pci 1e.0 off end # UART #0 + device pci 1e.1 off end # UART #1 + device pci 1e.2 off end # GSPI #0 + device pci 1e.3 off end # GSPI #1 + device pci 1f.0 on end # LPC Interface + device pci 1f.1 on end # P2SB + device pci 1f.2 on end # Power Management Controller + device pci 1f.3 on end # Intel HDA + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # PCH SPI + device pci 1f.6 on end # GbE + end +end diff --git a/src/mainboard/siemens/field_pg_m6/variants/base/gpio.c b/src/mainboard/siemens/field_pg_m6/variants/base/gpio.c new file mode 100644 index 0000000..005d12c --- /dev/null +++ b/src/mainboard/siemens/field_pg_m6/variants/base/gpio.c @@ -0,0 +1,132 @@ +/* + * SPDX-License-Identifier: GPL-2.0-only + * This file is part of the coreboot project. + */ + +#include <soc/gpio.h> +#include "variant.h" + +static const struct pad_config gpio_table[] = { +/* GPP_A14 GPIO 0x0000002644000300 */ PAD_NC(GPP_A14, NONE), +/* GPP_A16 GPIO 0x0000002444000300 */ PAD_NC(GPP_A16, DN_20K), +/* GPP_B4 GPIO 0x0000003444000200 */ PAD_CFG_GPO(GPP_B4, 0, DEEP), +/* GPP_B5 GPIO 0x0000003544000300 */ PAD_NC(GPP_B5, NONE), +/* GPP_B6 GPIO 0x0000003644000300 */ PAD_NC(GPP_B6, NONE), +/* GPP_B8 GPIO 0x0000003844000300 */ PAD_NC(GPP_B8, NONE), +/* GPP_B10 GPIO 0x0000003a44000300 */ PAD_NC(GPP_B10, NONE), +/* GPP_B11 GPIO 0x0000003b44000201 */ PAD_CFG_GPO(GPP_B11, 1, DEEP), +/* GPP_B14 SPKR 0x0000003e44000600 */ PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), +/* GPP_B18 GPIO 0x0000004244000300 */ PAD_NC(GPP_B18, NONE), +/* GPP_B22 GPIO 0x0000004644000300 */ PAD_NC(GPP_B22, NONE), +/* GPP_C2 GPIO 0x0000004a44000300 */ PAD_NC(GPP_C2, NONE), +/* GPP_C5 GPIO 0x0000004d44000300 */ PAD_NC(GPP_C5, NONE), +/* GPP_C6 SML1CLK 0x0000004e44000703 */ PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), +/* GPP_C7 SML1DATA 0x0000004f44000703 */ PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), +/* GPP_C8 GPIO 0x0000005044000300 */ PAD_NC(GPP_C8, NONE), +/* GPP_C9 GPIO 0x0000005144000300 */ PAD_NC(GPP_C9, NONE), +/* GPP_C12 GPIO 0x0000005444000102 */ PAD_CFG_GPI(GPP_C12, NONE, DEEP), +/* GPP_C13 GPIO 0x0000005544000102 */ PAD_CFG_GPI(GPP_C13, NONE, DEEP), +/* GPP_C14 GPIO 0x0000005644000102 */ PAD_CFG_GPI(GPP_C14, NONE, DEEP), +/* GPP_C15 GPIO 0x0000005744000100 */ PAD_CFG_GPI(GPP_C15, NONE, DEEP), +/* GPP_C16 I2C0_SDA 0x0000005884800402 */ PAD_CFG_NF(GPP_C16, NONE, PLTRST, NF1), +/* GPP_C17 I2C0_SCL 0x0000005944000602 */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), +/* GPP_C20 UART2_RXD 0x0000005c44000500 */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), +/* GPP_C21 UART2_TXD 0x0000005d44000600 */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), +/* GPP_C22 UART2_RTS# 0x0000005e44000500 */ PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1), +/* GPP_C23 UART2_CTS# 0x0000005f44000502 */ PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1), +/* GPP_D1 GPIO 0x0000006144000102 */ PAD_CFG_GPI(GPP_D1, NONE, DEEP), +/* GPP_D2 GPIO 0x0000006244800102 */ PAD_CFG_GPI(GPP_D2, NONE, DEEP), +/* GPP_D3 GPIO 0x0000006344000201 */ PAD_CFG_GPO(GPP_D3, 1, DEEP), +/* GPP_D7 GPIO 0x0000006784000102 */ PAD_CFG_GPI(GPP_D7, NONE, PLTRST), +/* GPP_D8 GPIO 0x0000006884000100 */ PAD_CFG_GPI(GPP_D8, NONE, PLTRST), +/* GPP_D17 DMIC_CLK1 0x0000007144000700 */ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), +/* GPP_D18 DMIC_DATA1 0x0000007244000700 */ PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), +/* GPP_D19 DMIC_CLK0 0x0000007344000700 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), +/* GPP_D20 DMIC_DATA0 0x0000007444000700 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), +/* GPP_D21 GPIO 0x0000007544000201 */ PAD_CFG_GPO(GPP_D21, 1, DEEP), +/* GPP_D22 GPIO 0x0000007644800100 */ PAD_CFG_GPI(GPP_D22, NONE, DEEP), +/* GPP_G1 GPIO 0x0000006d84000201 */ PAD_CFG_GPO(GPP_G1, 1, PLTRST), +/* GPP_G2 GPIO 0x0000006e84800102 */ PAD_CFG_GPI(GPP_G2, NONE, PLTRST), +/* GPP_G3 GPIO 0x0000006f40880102 */ PAD_CFG_GPI_APIC(GPP_G3, NONE, DEEP, LEVEL, INVERT), +/* GPIO_RSVD_9 GPIO 0x0000000040000300 */ PAD_NC(GPIO_RSVD_9, NONE), +/* GPIO_RSVD_10 GPIO 0x0000000040000300 */ PAD_NC(GPIO_RSVD_10, NONE), +/* GPD0 BATLOW# 0x0000006044000702 */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), +/* GPD1 ACPRESENT 0x00003c6144000502 */ PAD_CFG_NF(GPD1, NATIVE, DEEP, NF1), +/* GPD7 GPIO 0x00000067c4000200 */ PAD_CFG_GPO(GPD7, 0, RSMRST), +/* GPP_K0 GPIO 0x0000001884000102 */ PAD_CFG_GPI(GPP_K0, NONE, PLTRST), +/* GPP_K1 GPIO 0x0000001984000100 */ PAD_CFG_GPI(GPP_K1, NONE, PLTRST), +/* GPP_K2 GPIO 0x0000001a84000100 */ PAD_CFG_GPI(GPP_K2, NONE, PLTRST), +/* GPP_K3 GPIO 0x0000001b84000102 */ PAD_CFG_GPI(GPP_K3, NONE, PLTRST), +/* GPP_K4 GPIO 0x0000001c04000201 */ PAD_CFG_GPO(GPP_K4, 1, PWROK), +/* GPP_K5 GPIO 0x0000001d04000201 */ PAD_CFG_GPO(GPP_K5, 1, PWROK), +/* GPP_K8 GPIO 0x0000002044000300 */ PAD_NC(GPP_K8, NONE), +/* GPP_K9 GPIO 0x0000002144000300 */ PAD_NC(GPP_K9, NONE), +/* GPP_K10 GPIO 0x0000002244000300 */ PAD_NC(GPP_K10, NONE), +/* GPP_K11 GPIO 0x0000002344000300 */ PAD_NC(GPP_K11, NONE), +/* GPP_K20 GPIO 0x0000002c84000201 */ PAD_CFG_GPO(GPP_K20, 1, PLTRST), +/* GPP_K21 GPIO 0x0000002d44000300 */ PAD_NC(GPP_K21, NONE), +/* GPP_H0 GPIO 0x0000004884000102 */ PAD_CFG_GPI(GPP_H0, NONE, PLTRST), +/* GPP_H2 GPIO 0x0000004a44000300 */ PAD_NC(GPP_H2, NONE), +/* GPP_H3 GPIO 0x0000004b44000300 */ PAD_NC(GPP_H3, NONE), +/* GPP_H10 GPIO 0x0000005244800102 */ PAD_CFG_GPI(GPP_H10, NONE, DEEP), +/* GPP_H15 GPIO 0x0000005744000201 */ PAD_CFG_GPO(GPP_H15, 1, DEEP), +/* GPP_H17 GPIO 0x0000005944000201 */ PAD_CFG_GPO(GPP_H17, 1, DEEP), +/* GPP_E0 SATAXPCIE0 0x0000001844800502 */ PAD_CFG_NF(GPP_E0, NONE, DEEP, NF1), +/* GPP_E1 GPIO 0x0000001944000300 */ PAD_NC(GPP_E1, NONE), +/* GPP_E2 GPIO 0x0000001a44000300 */ PAD_NC(GPP_E2, NONE), +/* GPP_E4 SATA_DEVSLP0 0x0000001c44000600 */ PAD_CFG_NF(GPP_E4, NONE, DEEP, NF1), +/* GPP_E5 GPIO 0x0000301d44800102 */ PAD_CFG_GPI(GPP_E5, NONE, DEEP), +/* GPP_E6 GPIO 0x0000001e44800102 */ PAD_CFG_GPI(GPP_E6, NONE, DEEP), +/* GPP_E8 SATALED# 0x0000002044000700 */ PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), +/* GPP_E9 USB2_OC0# 0x0000302144000702 */ PAD_CFG_NF(GPP_E9, UP_20K, DEEP, NF1), +/* GPP_E10 USB2_OC1# 0x0000302244000702 */ PAD_CFG_NF(GPP_E10, UP_20K, DEEP, NF1), +/* GPP_E11 USB2_OC2# 0x0000302344000702 */ PAD_CFG_NF(GPP_E11, UP_20K, DEEP, NF1), +/* GPP_E12 GPIO 0x0000002484000201 */ PAD_CFG_GPO(GPP_E12, 1, PLTRST), +/* GPP_F1 GPIO 0x0000003144000300 */ PAD_NC(GPP_F1, NONE), +/* GPP_F2 GPIO 0x0000003244000300 */ PAD_NC(GPP_F2, NONE), +/* GPP_F3 GPIO 0x0000003344000300 */ PAD_NC(GPP_F3, NONE), +/* GPP_F4 GPIO 0x0000003444000300 */ PAD_NC(GPP_F4, NONE), +/* GPP_F5 GPIO 0x0000003584000201 */ PAD_CFG_GPO(GPP_F5, 1, PLTRST), +/* GPP_F6 SATA_DEVSLP4 0x0000003644000700 */ PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), +/* GPP_F8 GPIO 0x0000003844800000 */ PAD_CFG_GPO(GPP_F8, 0, DEEP), +/* GPP_F9 GPIO 0x0000003944000200 */ PAD_CFG_GPO(GPP_F9, 0, DEEP), +/* GPP_F10 GPIO 0x0000003a84000100 */ PAD_CFG_GPI(GPP_F10, NONE, PLTRST), +/* GPP_F13 GPIO 0x0000003d82800102 */ PAD_CFG_GPI(GPP_F13, NONE, PLTRST), +/* GPP_F14 GPIO 0x0000003e44000300 */ PAD_NC(GPP_F14, NONE), +/* GPP_F15 USB2_OC4# 0x0000303f44000702 */ PAD_CFG_NF(GPP_F15, UP_20K, DEEP, NF1), +/* GPP_F16 USB2_OC5# 0x0000304044000702 */ PAD_CFG_NF(GPP_F16, UP_20K, DEEP, NF1), +/* GPP_F17 USB2_OC6# 0x0000304144000702 */ PAD_CFG_NF(GPP_F17, UP_20K, DEEP, NF1), +/* GPP_F18 GPIO 0x0000004240880102 */ PAD_CFG_GPI_APIC(GPP_F18, NONE, DEEP, LEVEL, INVERT), +/* GPP_F19 eDP_VDDEN 0x0000004344000700 */ PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), +/* GPP_F20 eDP_BKLTEN 0x0000004444000700 */ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), +/* GPP_F21 eDP_BKLTCTL 0x0000004544000700 */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), +/* GPP_F22 DDPF_CTRLCLK 0x0000004644000700 */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), +/* GPP_F23 DDPF_CTRLDATA 0x0000004744000702 */ PAD_CFG_NF(GPP_F23, NONE, DEEP, NF1), +/* GPP_I0 DDPB_HPD0 0x00003c0040000700 */ PAD_CFG_NF(GPP_I0, NATIVE, DEEP, NF1), +/* GPP_I1 DDPB_HPD1 0x00003c0040000700 */ PAD_CFG_NF(GPP_I1, NATIVE, DEEP, NF1), +/* GPP_I2 DDPB_HPD2 0x00003c0040000700 */ PAD_CFG_NF(GPP_I2, NATIVE, DEEP, NF1), +/* GPP_I3 DDPB_HPD3 0x0000000040000700 */ PAD_CFG_NF(GPP_I3, NONE, DEEP, NF1), +/* GPP_I4 EDP_HPD 0x0000000040000700 */ PAD_CFG_NF(GPP_I4, NONE, DEEP, NF1), +/* GPP_I5 DDPB_CTRLCLK 0x0000000040000700 */ PAD_CFG_NF(GPP_I5, NONE, DEEP, NF1), +/* GPP_I6 DDPB_CTRLDATA 0x0000000040000702 */ PAD_CFG_NF(GPP_I6, NONE, DEEP, NF1), +/* GPP_I7 DDPC_CTRLCLK 0x0000000040000700 */ PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1), +/* GPP_I8 DDPC_CTRLDATA 0x0000000040000700 */ PAD_CFG_NF(GPP_I8, NONE, DEEP, NF1), +/* GPP_I9 DDPD_CTRLCLK 0x0000100040000700 */ PAD_CFG_NF(GPP_I9, DN_20K, DEEP, NF1), +/* GPP_I10 DDPD_CTRLDATA 0x0000100040000700 */ PAD_CFG_NF(GPP_I10, DN_20K, DEEP, NF1), +/* GPP_J2 n/a 0x0000003044000700 */ PAD_CFG_NF(GPP_J2, NONE, DEEP, NF1), +/* GPP_J3 n/a 0x0000003144000700 */ PAD_CFG_NF(GPP_J3, NONE, DEEP, NF1), +/* GPP_J4 CNV_BRI_DT 0x0000003244000702 */ PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1), +/* GPP_J5 CNV_BRI_RSP 0x0000003344000702 */ PAD_CFG_NF(GPP_J5, NONE, DEEP, NF1), +/* GPP_J6 CNV_RGI_DT 0x0000003444000700 */ PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1), +/* GPP_J7 CNV_RGI_RSP 0x0000003544000700 */ PAD_CFG_NF(GPP_J7, NONE, DEEP, NF1), +/* GPP_J8 CNV_MFUART2_RXD 0x0000003644000602 */ PAD_CFG_NF(GPP_J8, NONE, DEEP, NF1), +/* GPP_J9 CNV_MFUART2_TXD 0x0000003744000702 */ PAD_CFG_NF(GPP_J9, NONE, DEEP, NF1), +/* GPP_J10 n/a 0x0000003844000602 */ PAD_CFG_NF(GPP_J10, NONE, DEEP, NF1), +/* GPP_J11 A4WP_PRESENT 0x0000003944000700 */ PAD_CFG_NF(GPP_J11, NONE, DEEP, NF1), +}; + +const struct pad_config *variant_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +}
Sebastian Witt has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39976 )
Change subject: mb/siemens/field_pg_m6: Add new mainboard ......................................................................
Patch Set 6:
(2 comments)
Hi,
some clarification on BOOMER and the EC. And is this the Field PG M6 hardware or some variation of it?
Regards, Sebastian
https://review.coreboot.org/c/coreboot/+/39976/6/src/mainboard/siemens/field... File src/mainboard/siemens/field_pg_m6/ec.c:
https://review.coreboot.org/c/coreboot/+/39976/6/src/mainboard/siemens/field... PS6, Line 16: BOOMER
The chip is some H8, IIRC. I had little information when writing this, […]
BOOMER_ON enables the sound amplifier for the speakers. The EC is a H8S2113R.
https://review.coreboot.org/c/coreboot/+/39976/6/src/mainboard/siemens/field... File src/mainboard/siemens/field_pg_m6/variants/base/board_info.txt:
https://review.coreboot.org/c/coreboot/+/39976/6/src/mainboard/siemens/field... PS6, Line 1: Board name: Field PG M6 Is this really the Siemens Field PG M6 (hardware) or some variation of it?
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39976 )
Change subject: mb/siemens/field_pg_m6: Add new mainboard ......................................................................
Patch Set 6:
(2 comments)
https://review.coreboot.org/c/coreboot/+/39976/6/src/mainboard/siemens/field... File src/mainboard/siemens/field_pg_m6/ec.c:
https://review.coreboot.org/c/coreboot/+/39976/6/src/mainboard/siemens/field... PS6, Line 16: BOOMER
BOOMER_ON enables the sound amplifier for the speakers. The EC is a H8S2113R.
Hello Sebastian, thanks for the clarification :)
https://review.coreboot.org/c/coreboot/+/39976/6/src/mainboard/siemens/field... File src/mainboard/siemens/field_pg_m6/variants/base/board_info.txt:
https://review.coreboot.org/c/coreboot/+/39976/6/src/mainboard/siemens/field... PS6, Line 1: Board name: Field PG M6
Is this really the Siemens Field PG M6 (hardware) or some variation of it?
AFAIK, it was the original board (I didn't get a whole machine). The "base" variant should be able to boot. But all the PG's special interfaces and laptop functions were ignored. So if some of these work, it's sheer luck.
Nico Huber has uploaded a new patch set (#7) to the change originally created by Felix Singer. ( https://review.coreboot.org/c/coreboot/+/39976 )
Change subject: mb/siemens/field_pg_m6: Add new mainboard ......................................................................
mb/siemens/field_pg_m6: Add new mainboard
The Field PG is a ruggedized laptop with additional industrial interfaces. So far, only booting and basic interfaces (USB, UART, Video) are working with the original model, the "base" variant. No further development is planned for this variant, as our primary target was another one that will be added in a follow-up.
Change-Id: I1d3508b615ec877edc8db756e9ad38132b37219c Signed-off-by: Thomas Heijligen thomas.heijligen@secunet.com Signed-off-by: Nico Huber nico.huber@secunet.com Signed-off-by: Felix Singer felix.singer@secunet.com --- A src/mainboard/siemens/field_pg_m6/Kconfig A src/mainboard/siemens/field_pg_m6/Kconfig.name A src/mainboard/siemens/field_pg_m6/Makefile.inc A src/mainboard/siemens/field_pg_m6/board_info.txt A src/mainboard/siemens/field_pg_m6/cmos.layout A src/mainboard/siemens/field_pg_m6/dsdt.asl A src/mainboard/siemens/field_pg_m6/ec.c A src/mainboard/siemens/field_pg_m6/ec.h A src/mainboard/siemens/field_pg_m6/mainboard.c A src/mainboard/siemens/field_pg_m6/romstage.c A src/mainboard/siemens/field_pg_m6/variant.h A src/mainboard/siemens/field_pg_m6/variants/base/Makefile.inc A src/mainboard/siemens/field_pg_m6/variants/base/board_info.txt A src/mainboard/siemens/field_pg_m6/variants/base/data.vbt A src/mainboard/siemens/field_pg_m6/variants/base/devicetree.cb A src/mainboard/siemens/field_pg_m6/variants/base/gma-mainboard.ads A src/mainboard/siemens/field_pg_m6/variants/base/gpio.c 17 files changed, 657 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/39976/7
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39976 )
Change subject: mb/siemens/field_pg_m6: Add new mainboard ......................................................................
Patch Set 7: Code-Review+1
Sebastian Witt has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39976 )
Change subject: mb/siemens/field_pg_m6: Add new mainboard ......................................................................
Patch Set 7:
(1 comment)
Info about boards/name
https://review.coreboot.org/c/coreboot/+/39976/6/src/mainboard/siemens/field... File src/mainboard/siemens/field_pg_m6/variants/base/board_info.txt:
https://review.coreboot.org/c/coreboot/+/39976/6/src/mainboard/siemens/field... PS6, Line 1: Board name: Field PG M6
AFAIK, it was the original board (I didn't get a whole machine). The "base" […]
There are two different boards, they may have the same chipset and CPU, but the used interfaces (LAN, USB, SATA, M.2, ...) are different and not completely compatible. The one in the PG M6 is a smaller one.
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39976 )
Change subject: mb/siemens/field_pg_m6: Add new mainboard ......................................................................
Patch Set 7:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39976/6/src/mainboard/siemens/field... File src/mainboard/siemens/field_pg_m6/variants/base/board_info.txt:
https://review.coreboot.org/c/coreboot/+/39976/6/src/mainboard/siemens/field... PS6, Line 1: Board name: Field PG M6
There are two different boards, they may have the same chipset and CPU, but the used interfaces (LAN […]
Well, "Field PG M6" is what it said on all the documentation. And the block diagramm matched what was on the board. What is the other board called?
If you ever want to try this on your hardware and are uncertain, `variants/base/gpio.c` contains the most delicate settings that should be checked (against schematics, for instance). Everything else shouldn't be able to cause any harm.
Siemens built another variant for us, codenamed Chili (CB:39995), and there may follow more.
Hello build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth, Paul Menzel, Thomas Heijligen, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39976
to look at the new patch set (#8).
Change subject: mb/siemens/field_pg_m6: Add new mainboard ......................................................................
mb/siemens/field_pg_m6: Add new mainboard
The Field PG is a ruggedized laptop with additional industrial interfaces. So far, only booting and basic interfaces (USB, UART, Video) are working with the original model, the "base" variant. No further development is planned for this variant, as our primary target was another one that will be added in a follow-up.
Change-Id: I1d3508b615ec877edc8db756e9ad38132b37219c Signed-off-by: Thomas Heijligen thomas.heijligen@secunet.com Signed-off-by: Nico Huber nico.huber@secunet.com Signed-off-by: Felix Singer felix.singer@secunet.com --- A src/mainboard/siemens/field_pg_m6/Kconfig A src/mainboard/siemens/field_pg_m6/Kconfig.name A src/mainboard/siemens/field_pg_m6/Makefile.inc A src/mainboard/siemens/field_pg_m6/board_info.txt A src/mainboard/siemens/field_pg_m6/cmos.layout A src/mainboard/siemens/field_pg_m6/dsdt.asl A src/mainboard/siemens/field_pg_m6/ec.c A src/mainboard/siemens/field_pg_m6/ec.h A src/mainboard/siemens/field_pg_m6/mainboard.c A src/mainboard/siemens/field_pg_m6/romstage.c A src/mainboard/siemens/field_pg_m6/variant.h A src/mainboard/siemens/field_pg_m6/variants/base/Makefile.inc A src/mainboard/siemens/field_pg_m6/variants/base/board_info.txt A src/mainboard/siemens/field_pg_m6/variants/base/data.vbt A src/mainboard/siemens/field_pg_m6/variants/base/devicetree.cb A src/mainboard/siemens/field_pg_m6/variants/base/gma-mainboard.ads A src/mainboard/siemens/field_pg_m6/variants/base/gpio.c 17 files changed, 657 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/39976/8
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39976 )
Change subject: mb/siemens/field_pg_m6: Add new mainboard ......................................................................
Patch Set 8:
(2 comments)
https://review.coreboot.org/c/coreboot/+/39976/8/src/mainboard/siemens/field... File src/mainboard/siemens/field_pg_m6/variants/base/gpio.c:
https://review.coreboot.org/c/coreboot/+/39976/8/src/mainboard/siemens/field... PS8, Line 48: /* GPP_G3 GPIO 0x0000006f40880102 */ PAD_CFG_GPI_APIC(GPP_G3, NONE, DEEP, LEVEL, INVERT), line over 96 characters
https://review.coreboot.org/c/coreboot/+/39976/8/src/mainboard/siemens/field... PS8, Line 97: /* GPP_F18 GPIO 0x0000004240880102 */ PAD_CFG_GPI_APIC(GPP_F18, NONE, DEEP, LEVEL, INVERT), line over 96 characters
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39976 )
Change subject: mb/siemens/field_pg_m6: Add new mainboard ......................................................................
Patch Set 9:
(2 comments)
https://review.coreboot.org/c/coreboot/+/39976/9/src/mainboard/siemens/field... File src/mainboard/siemens/field_pg_m6/variants/base/gpio.c:
https://review.coreboot.org/c/coreboot/+/39976/9/src/mainboard/siemens/field... PS9, Line 48: /* GPP_G3 GPIO 0x0000006f40880102 */ PAD_CFG_GPI_APIC(GPP_G3, NONE, DEEP, LEVEL, INVERT), line over 96 characters
https://review.coreboot.org/c/coreboot/+/39976/9/src/mainboard/siemens/field... PS9, Line 97: /* GPP_F18 GPIO 0x0000004240880102 */ PAD_CFG_GPI_APIC(GPP_F18, NONE, DEEP, LEVEL, INVERT), line over 96 characters
Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39976 )
Change subject: mb/siemens/field_pg_m6: Add new mainboard ......................................................................
Patch Set 9:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39976/6/src/mainboard/siemens/field... File src/mainboard/siemens/field_pg_m6/cmos.layout:
https://review.coreboot.org/c/coreboot/+/39976/6/src/mainboard/siemens/field... PS6, Line 56: 5 0 Disable
nit: move this to ID #2?
Done
Hello build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth, Paul Menzel, Thomas Heijligen, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39976
to look at the new patch set (#10).
Change subject: mb/siemens/field_pg_m6: Add new mainboard ......................................................................
mb/siemens/field_pg_m6: Add new mainboard
The Field PG is a ruggedized laptop with additional industrial interfaces. So far, only booting and basic interfaces (USB, UART, Video) are working with the original model, the "base" variant. No further development is planned for this variant, as our primary target was another one that will be added in a follow-up.
Change-Id: I1d3508b615ec877edc8db756e9ad38132b37219c Signed-off-by: Thomas Heijligen thomas.heijligen@secunet.com Signed-off-by: Nico Huber nico.huber@secunet.com Signed-off-by: Felix Singer felix.singer@secunet.com --- A src/mainboard/siemens/field_pg_m6/Kconfig A src/mainboard/siemens/field_pg_m6/Kconfig.name A src/mainboard/siemens/field_pg_m6/Makefile.inc A src/mainboard/siemens/field_pg_m6/board_info.txt A src/mainboard/siemens/field_pg_m6/cmos.layout A src/mainboard/siemens/field_pg_m6/dsdt.asl A src/mainboard/siemens/field_pg_m6/ec.c A src/mainboard/siemens/field_pg_m6/ec.h A src/mainboard/siemens/field_pg_m6/mainboard.c A src/mainboard/siemens/field_pg_m6/romstage.c A src/mainboard/siemens/field_pg_m6/variant.h A src/mainboard/siemens/field_pg_m6/variants/base/Makefile.inc A src/mainboard/siemens/field_pg_m6/variants/base/board_info.txt A src/mainboard/siemens/field_pg_m6/variants/base/data.vbt A src/mainboard/siemens/field_pg_m6/variants/base/devicetree.cb A src/mainboard/siemens/field_pg_m6/variants/base/gma-mainboard.ads A src/mainboard/siemens/field_pg_m6/variants/base/gpio.c 17 files changed, 657 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/39976/10
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39976 )
Change subject: mb/siemens/field_pg_m6: Add new mainboard ......................................................................
Patch Set 10:
(2 comments)
https://review.coreboot.org/c/coreboot/+/39976/10/src/mainboard/siemens/fiel... File src/mainboard/siemens/field_pg_m6/variants/base/gpio.c:
https://review.coreboot.org/c/coreboot/+/39976/10/src/mainboard/siemens/fiel... PS10, Line 48: /* GPP_G3 GPIO 0x0000006f40880102 */ PAD_CFG_GPI_APIC(GPP_G3, NONE, DEEP, LEVEL, INVERT), line over 96 characters
https://review.coreboot.org/c/coreboot/+/39976/10/src/mainboard/siemens/fiel... PS10, Line 97: /* GPP_F18 GPIO 0x0000004240880102 */ PAD_CFG_GPI_APIC(GPP_F18, NONE, DEEP, LEVEL, INVERT), line over 96 characters
Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39976 )
Change subject: mb/siemens/chili: Add new mainboard ......................................................................
Set Ready For Review
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39976 )
Change subject: mb/siemens/chili: Add new mainboard ......................................................................
Patch Set 31:
(3 comments)
https://review.coreboot.org/c/coreboot/+/39976/31/src/mainboard/siemens/chil... File src/mainboard/siemens/chili/mainboard.c:
https://review.coreboot.org/c/coreboot/+/39976/31/src/mainboard/siemens/chil... PS31, Line 5: <acpi/acpi.h> maybe not used ?
https://review.coreboot.org/c/coreboot/+/39976/31/src/mainboard/siemens/chil... PS31, Line 11: e <pc80/mc146818rtc.h> maybe not used.
please check the other includes
https://review.coreboot.org/c/coreboot/+/39976/31/src/mainboard/siemens/chil... File src/mainboard/siemens/chili/romstage.c:
https://review.coreboot.org/c/coreboot/+/39976/31/src/mainboard/siemens/chil... PS31, Line 6: <pc80/mc146818rtc.h> not used?
Hello build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth, Paul Menzel, Thomas Heijligen, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39976
to look at the new patch set (#32).
Change subject: mb/siemens/chili: Add new mainboard ......................................................................
mb/siemens/chili: Add new mainboard
The Chili base board is a ruggedized laptop with additional industrial interfaces. So far, only booting and basic interfaces (USB, UART, Video) are working with the original model, the "base" variant. No further development is planned for this variant, as our primary target was another one that will be added in a follow-up.
Change-Id: I1d3508b615ec877edc8db756e9ad38132b37219c Signed-off-by: Thomas Heijligen thomas.heijligen@secunet.com Signed-off-by: Nico Huber nico.huber@secunet.com Signed-off-by: Felix Singer felix.singer@secunet.com --- A src/mainboard/siemens/chili/Kconfig A src/mainboard/siemens/chili/Kconfig.name A src/mainboard/siemens/chili/Makefile.inc A src/mainboard/siemens/chili/board_info.txt A src/mainboard/siemens/chili/cmos.layout A src/mainboard/siemens/chili/dsdt.asl A src/mainboard/siemens/chili/ec.c A src/mainboard/siemens/chili/ec.h A src/mainboard/siemens/chili/mainboard.c A src/mainboard/siemens/chili/romstage.c A src/mainboard/siemens/chili/variant.h A src/mainboard/siemens/chili/variants/base/Makefile.inc A src/mainboard/siemens/chili/variants/base/board_info.txt A src/mainboard/siemens/chili/variants/base/data.vbt A src/mainboard/siemens/chili/variants/base/devicetree.cb A src/mainboard/siemens/chili/variants/base/gma-mainboard.ads A src/mainboard/siemens/chili/variants/base/gpio.c 17 files changed, 647 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/39976/32
Hello build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth, Paul Menzel, Thomas Heijligen, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39976
to look at the new patch set (#33).
Change subject: mb/siemens/chili: Add new mainboard ......................................................................
mb/siemens/chili: Add new mainboard
The Chili base board is a ruggedized laptop with additional industrial interfaces. So far, only booting and basic interfaces (USB, UART, Video) are working with the original model, the "base" variant. No further development is planned for this variant, as our primary target was another one that will be added in a follow-up.
Change-Id: I1d3508b615ec877edc8db756e9ad38132b37219c Signed-off-by: Thomas Heijligen thomas.heijligen@secunet.com Signed-off-by: Nico Huber nico.huber@secunet.com Signed-off-by: Felix Singer felix.singer@secunet.com --- A src/mainboard/siemens/chili/Kconfig A src/mainboard/siemens/chili/Kconfig.name A src/mainboard/siemens/chili/Makefile.inc A src/mainboard/siemens/chili/board_info.txt A src/mainboard/siemens/chili/cmos.layout A src/mainboard/siemens/chili/dsdt.asl A src/mainboard/siemens/chili/ec.c A src/mainboard/siemens/chili/ec.h A src/mainboard/siemens/chili/mainboard.c A src/mainboard/siemens/chili/romstage.c A src/mainboard/siemens/chili/variant.h A src/mainboard/siemens/chili/variants/base/Makefile.inc A src/mainboard/siemens/chili/variants/base/board_info.txt A src/mainboard/siemens/chili/variants/base/data.vbt A src/mainboard/siemens/chili/variants/base/devicetree.cb A src/mainboard/siemens/chili/variants/base/gma-mainboard.ads A src/mainboard/siemens/chili/variants/base/gpio.c 17 files changed, 637 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/39976/33
Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39976 )
Change subject: mb/siemens/chili: Add new mainboard ......................................................................
Patch Set 33:
(3 comments)
https://review.coreboot.org/c/coreboot/+/39976/31/src/mainboard/siemens/chil... File src/mainboard/siemens/chili/mainboard.c:
https://review.coreboot.org/c/coreboot/+/39976/31/src/mainboard/siemens/chil... PS31, Line 5: <acpi/acpi.h>
maybe not used ?
Done
https://review.coreboot.org/c/coreboot/+/39976/31/src/mainboard/siemens/chil... PS31, Line 11: e <pc80/mc146818rtc.h>
maybe not used. […]
Done
https://review.coreboot.org/c/coreboot/+/39976/31/src/mainboard/siemens/chil... File src/mainboard/siemens/chili/romstage.c:
https://review.coreboot.org/c/coreboot/+/39976/31/src/mainboard/siemens/chil... PS31, Line 6: <pc80/mc146818rtc.h>
not used?
Done
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39976 )
Change subject: mb/siemens/chili: Add new mainboard ......................................................................
Patch Set 33:
(3 comments)
https://review.coreboot.org/c/coreboot/+/39976/12/src/mainboard/siemens/chil... File src/mainboard/siemens/chili/variants/base/gma-mainboard.ads:
https://review.coreboot.org/c/coreboot/+/39976/12/src/mainboard/siemens/chil... PS12, Line 12: -- For a three-pipe setup, bandwidth is shared between the 2nd and
We discussed this with Nico, and it's apparently a limitation of platforms with Ivy Bridge. […]
Sorry, that's probably my copy-pasta. Please remove the whole comment.
Actually, the whole file is copy-pasta. Please update. CFL doesn't have `Analog` at all. I only recall a single DP (potentially DP++ with HDMI capability) and eDP.
https://review.coreboot.org/c/coreboot/+/39976/6/src/mainboard/siemens/field... File src/mainboard/siemens/field_pg_m6/ec.c:
https://review.coreboot.org/c/coreboot/+/39976/6/src/mainboard/siemens/field... PS6, Line 16: BOOMER
Hello Sebastian, thanks for the clarification :)
Angel, is it ok to resolve this without adding comments? I think the macro names explain themself when one has the device at hand (at least as far as I could comment them anyway). The EC chip model really shouldn't matter.
https://review.coreboot.org/c/coreboot/+/39976/6/src/mainboard/siemens/field... File src/mainboard/siemens/field_pg_m6/variants/base/board_info.txt:
https://review.coreboot.org/c/coreboot/+/39976/6/src/mainboard/siemens/field... PS6, Line 1: Board name: Field PG M6
Well, "Field PG M6" is what it said on all the documentation. And the […]
Board name has been reduce to "Chili base board" in the meantime.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39976 )
Change subject: mb/siemens/chili: Add new mainboard ......................................................................
Patch Set 33:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39976/6/src/mainboard/siemens/field... File src/mainboard/siemens/field_pg_m6/ec.c:
https://review.coreboot.org/c/coreboot/+/39976/6/src/mainboard/siemens/field... PS6, Line 16: BOOMER
Angel, is it ok to resolve this without adding comments? I think the […]
I'm fine with it. If anything, I can always refer to this comment thread.
Hello build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth, Paul Menzel, Thomas Heijligen, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39976
to look at the new patch set (#34).
Change subject: mb/siemens/chili: Add new mainboard ......................................................................
mb/siemens/chili: Add new mainboard
The Chili base board is a ruggedized laptop with additional industrial interfaces. So far, only booting and basic interfaces (USB, UART, Video) are working with the original model, the "base" variant. No further development is planned for this variant, as our primary target was another one that will be added in a follow-up.
Change-Id: I1d3508b615ec877edc8db756e9ad38132b37219c Signed-off-by: Thomas Heijligen thomas.heijligen@secunet.com Signed-off-by: Nico Huber nico.huber@secunet.com Signed-off-by: Felix Singer felix.singer@secunet.com --- A src/mainboard/siemens/chili/Kconfig A src/mainboard/siemens/chili/Kconfig.name A src/mainboard/siemens/chili/Makefile.inc A src/mainboard/siemens/chili/board_info.txt A src/mainboard/siemens/chili/cmos.layout A src/mainboard/siemens/chili/dsdt.asl A src/mainboard/siemens/chili/ec.c A src/mainboard/siemens/chili/ec.h A src/mainboard/siemens/chili/mainboard.c A src/mainboard/siemens/chili/romstage.c A src/mainboard/siemens/chili/variant.h A src/mainboard/siemens/chili/variants/base/Makefile.inc A src/mainboard/siemens/chili/variants/base/board_info.txt A src/mainboard/siemens/chili/variants/base/data.vbt A src/mainboard/siemens/chili/variants/base/devicetree.cb A src/mainboard/siemens/chili/variants/base/gma-mainboard.ads A src/mainboard/siemens/chili/variants/base/gpio.c 17 files changed, 631 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/39976/34
Hello build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth, Paul Menzel, Thomas Heijligen, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39976
to look at the new patch set (#35).
Change subject: mb/siemens/chili: Add new mainboard ......................................................................
mb/siemens/chili: Add new mainboard
The Chili base board is a ruggedized laptop with additional industrial interfaces. So far, only booting and basic interfaces (USB, UART, Video) are working with the original model, the "base" variant. No further development is planned for this variant, as our primary target was another one that will be added in a follow-up.
Change-Id: I1d3508b615ec877edc8db756e9ad38132b37219c Signed-off-by: Thomas Heijligen thomas.heijligen@secunet.com Signed-off-by: Nico Huber nico.huber@secunet.com Signed-off-by: Felix Singer felix.singer@secunet.com --- A src/mainboard/siemens/chili/Kconfig A src/mainboard/siemens/chili/Kconfig.name A src/mainboard/siemens/chili/Makefile.inc A src/mainboard/siemens/chili/board_info.txt A src/mainboard/siemens/chili/cmos.layout A src/mainboard/siemens/chili/dsdt.asl A src/mainboard/siemens/chili/ec.c A src/mainboard/siemens/chili/ec.h A src/mainboard/siemens/chili/mainboard.c A src/mainboard/siemens/chili/romstage.c A src/mainboard/siemens/chili/variant.h A src/mainboard/siemens/chili/variants/base/Makefile.inc A src/mainboard/siemens/chili/variants/base/board_info.txt A src/mainboard/siemens/chili/variants/base/data.vbt A src/mainboard/siemens/chili/variants/base/devicetree.cb A src/mainboard/siemens/chili/variants/base/gma-mainboard.ads A src/mainboard/siemens/chili/variants/base/gpio.c 17 files changed, 631 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/39976/35
Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39976 )
Change subject: mb/siemens/chili: Add new mainboard ......................................................................
Patch Set 35:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39976/12/src/mainboard/siemens/chil... File src/mainboard/siemens/chili/variants/base/gma-mainboard.ads:
https://review.coreboot.org/c/coreboot/+/39976/12/src/mainboard/siemens/chil... PS12, Line 12: -- For a three-pipe setup, bandwidth is shared between the 2nd and
Sorry, that's probably my copy-pasta. Please remove the whole comment. […]
Done
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39976 )
Change subject: mb/siemens/chili: Add new mainboard ......................................................................
Patch Set 35: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/39976/35/src/mainboard/siemens/chil... File src/mainboard/siemens/chili/cmos.layout:
https://review.coreboot.org/c/coreboot/+/39976/35/src/mainboard/siemens/chil... PS35, Line 26: 441 1 e 1 inhibit_flashlock This is gone from the upstreamed code, please remove.
Hello build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth, Paul Menzel, Thomas Heijligen, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39976
to look at the new patch set (#36).
Change subject: mb/siemens/chili: Add new mainboard ......................................................................
mb/siemens/chili: Add new mainboard
The Chili base board is a ruggedized laptop with additional industrial interfaces. So far, only booting and basic interfaces (USB, UART, Video) are working with the original model, the "base" variant. No further development is planned for this variant, as our primary target was another one that will be added in a follow-up.
Change-Id: I1d3508b615ec877edc8db756e9ad38132b37219c Signed-off-by: Thomas Heijligen thomas.heijligen@secunet.com Signed-off-by: Nico Huber nico.huber@secunet.com Signed-off-by: Felix Singer felix.singer@secunet.com --- A src/mainboard/siemens/chili/Kconfig A src/mainboard/siemens/chili/Kconfig.name A src/mainboard/siemens/chili/Makefile.inc A src/mainboard/siemens/chili/board_info.txt A src/mainboard/siemens/chili/cmos.layout A src/mainboard/siemens/chili/dsdt.asl A src/mainboard/siemens/chili/ec.c A src/mainboard/siemens/chili/ec.h A src/mainboard/siemens/chili/mainboard.c A src/mainboard/siemens/chili/romstage.c A src/mainboard/siemens/chili/variant.h A src/mainboard/siemens/chili/variants/base/Makefile.inc A src/mainboard/siemens/chili/variants/base/board_info.txt A src/mainboard/siemens/chili/variants/base/data.vbt A src/mainboard/siemens/chili/variants/base/devicetree.cb A src/mainboard/siemens/chili/variants/base/gma-mainboard.ads A src/mainboard/siemens/chili/variants/base/gpio.c 17 files changed, 630 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/39976/36
Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39976 )
Change subject: mb/siemens/chili: Add new mainboard ......................................................................
Patch Set 36:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39976/35/src/mainboard/siemens/chil... File src/mainboard/siemens/chili/cmos.layout:
https://review.coreboot.org/c/coreboot/+/39976/35/src/mainboard/siemens/chil... PS35, Line 26: 441 1 e 1 inhibit_flashlock
This is gone from the upstreamed code, please remove.
Done
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39976 )
Change subject: mb/siemens/chili: Add new mainboard ......................................................................
Patch Set 36: Code-Review+2
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39976 )
Change subject: mb/siemens/chili: Add new mainboard ......................................................................
Patch Set 36: Code-Review-1
Needs a final test, we had issues with Chili after a rebase.
Hello build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth, Paul Menzel, Thomas Heijligen, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39976
to look at the new patch set (#38).
Change subject: mb/siemens/chili: Add new mainboard ......................................................................
mb/siemens/chili: Add new mainboard
The Chili base board is a ruggedized laptop with additional industrial interfaces. So far, only booting and basic interfaces (USB, UART, Video) are working with the original model, the "base" variant. No further development is planned for this variant, as our primary target was another one that will be added in a follow-up.
Change-Id: I1d3508b615ec877edc8db756e9ad38132b37219c Signed-off-by: Thomas Heijligen thomas.heijligen@secunet.com Signed-off-by: Nico Huber nico.huber@secunet.com Signed-off-by: Felix Singer felix.singer@secunet.com --- A src/mainboard/siemens/chili/Kconfig A src/mainboard/siemens/chili/Kconfig.name A src/mainboard/siemens/chili/Makefile.inc A src/mainboard/siemens/chili/board_info.txt A src/mainboard/siemens/chili/cmos.layout A src/mainboard/siemens/chili/dsdt.asl A src/mainboard/siemens/chili/ec.c A src/mainboard/siemens/chili/ec.h A src/mainboard/siemens/chili/mainboard.c A src/mainboard/siemens/chili/romstage.c A src/mainboard/siemens/chili/variant.h A src/mainboard/siemens/chili/variants/base/Makefile.inc A src/mainboard/siemens/chili/variants/base/board_info.txt A src/mainboard/siemens/chili/variants/base/data.vbt A src/mainboard/siemens/chili/variants/base/devicetree.cb A src/mainboard/siemens/chili/variants/base/gma-mainboard.ads A src/mainboard/siemens/chili/variants/base/gpio.c 17 files changed, 630 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/39976/38
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39976 )
Change subject: mb/siemens/chili: Add new mainboard ......................................................................
Patch Set 38:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39976/38/src/mainboard/siemens/chil... File src/mainboard/siemens/chili/variants/base/gpio.c:
https://review.coreboot.org/c/coreboot/+/39976/38/src/mainboard/siemens/chil... PS38, Line 48: /* SPI0_CS1_B GPIO */ PAD_NC(SPI0_CS1_B, NONE), : /* SPI0_CLK GPIO */ PAD_NC(SPI0_CLK, NONE), Wrong settings after rebase.
Hello build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth, Paul Menzel, Thomas Heijligen, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39976
to look at the new patch set (#39).
Change subject: mb/siemens/chili: Add new mainboard ......................................................................
mb/siemens/chili: Add new mainboard
The Chili base board is a ruggedized laptop with additional industrial interfaces. So far, only booting and basic interfaces (USB, UART, Video) are working with the original model, the "base" variant. No further development is planned for this variant, as our primary target was another one that will be added in a follow-up.
Change-Id: I1d3508b615ec877edc8db756e9ad38132b37219c Signed-off-by: Thomas Heijligen thomas.heijligen@secunet.com Signed-off-by: Nico Huber nico.huber@secunet.com Signed-off-by: Felix Singer felix.singer@secunet.com --- A src/mainboard/siemens/chili/Kconfig A src/mainboard/siemens/chili/Kconfig.name A src/mainboard/siemens/chili/Makefile.inc A src/mainboard/siemens/chili/board_info.txt A src/mainboard/siemens/chili/cmos.layout A src/mainboard/siemens/chili/dsdt.asl A src/mainboard/siemens/chili/ec.c A src/mainboard/siemens/chili/ec.h A src/mainboard/siemens/chili/mainboard.c A src/mainboard/siemens/chili/romstage.c A src/mainboard/siemens/chili/variant.h A src/mainboard/siemens/chili/variants/base/Makefile.inc A src/mainboard/siemens/chili/variants/base/board_info.txt A src/mainboard/siemens/chili/variants/base/data.vbt A src/mainboard/siemens/chili/variants/base/devicetree.cb A src/mainboard/siemens/chili/variants/base/gma-mainboard.ads A src/mainboard/siemens/chili/variants/base/gpio.c 17 files changed, 630 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/39976/39
Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39976 )
Change subject: mb/siemens/chili: Add new mainboard ......................................................................
Patch Set 39:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39976/38/src/mainboard/siemens/chil... File src/mainboard/siemens/chili/variants/base/gpio.c:
https://review.coreboot.org/c/coreboot/+/39976/38/src/mainboard/siemens/chil... PS38, Line 48: /* SPI0_CS1_B GPIO */ PAD_NC(SPI0_CS1_B, NONE), : /* SPI0_CLK GPIO */ PAD_NC(SPI0_CLK, NONE),
Wrong settings after rebase.
Done
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39976 )
Change subject: mb/siemens/chili: Add new mainboard ......................................................................
Patch Set 39: Code-Review+2
Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39976 )
Change subject: mb/siemens/chili: Add new mainboard ......................................................................
Patch Set 39:
Felix, Nico, want to do another boot test or is this good to go in now?
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39976 )
Change subject: mb/siemens/chili: Add new mainboard ......................................................................
mb/siemens/chili: Add new mainboard
The Chili base board is a ruggedized laptop with additional industrial interfaces. So far, only booting and basic interfaces (USB, UART, Video) are working with the original model, the "base" variant. No further development is planned for this variant, as our primary target was another one that will be added in a follow-up.
Change-Id: I1d3508b615ec877edc8db756e9ad38132b37219c Signed-off-by: Thomas Heijligen thomas.heijligen@secunet.com Signed-off-by: Nico Huber nico.huber@secunet.com Signed-off-by: Felix Singer felix.singer@secunet.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/39976 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Angel Pons th3fanbus@gmail.com --- A src/mainboard/siemens/chili/Kconfig A src/mainboard/siemens/chili/Kconfig.name A src/mainboard/siemens/chili/Makefile.inc A src/mainboard/siemens/chili/board_info.txt A src/mainboard/siemens/chili/cmos.layout A src/mainboard/siemens/chili/dsdt.asl A src/mainboard/siemens/chili/ec.c A src/mainboard/siemens/chili/ec.h A src/mainboard/siemens/chili/mainboard.c A src/mainboard/siemens/chili/romstage.c A src/mainboard/siemens/chili/variant.h A src/mainboard/siemens/chili/variants/base/Makefile.inc A src/mainboard/siemens/chili/variants/base/board_info.txt A src/mainboard/siemens/chili/variants/base/data.vbt A src/mainboard/siemens/chili/variants/base/devicetree.cb A src/mainboard/siemens/chili/variants/base/gma-mainboard.ads A src/mainboard/siemens/chili/variants/base/gpio.c 17 files changed, 630 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved
diff --git a/src/mainboard/siemens/chili/Kconfig b/src/mainboard/siemens/chili/Kconfig new file mode 100644 index 0000000..8c919b5 --- /dev/null +++ b/src/mainboard/siemens/chili/Kconfig @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: GPL-2.0-only + +if BOARD_SIEMENS_CHILI_BASE + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_32768 + select DRIVERS_I2C_GENERIC + select DRIVERS_I2C_HID + select DRIVERS_UART_8250IO if BOARD_SIEMENS_CHILI_BASE + select EC_ACPI + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE + select INTEL_GMA_HAVE_VBT + select MAINBOARD_HAS_LIBGFXINIT + select MAINBOARD_HAS_LPC_TPM + select MAINBOARD_HAS_TPM2 + select MAINBOARD_USES_IFD_GBE_REGION + select SOC_INTEL_CANNONLAKE_PCH_H + select SOC_INTEL_COFFEELAKE + +config MAINBOARD_DIR + string + default "siemens/chili" + +config MAINBOARD_FAMILY + string + default "Chili" + +config MAINBOARD_PART_NUMBER + string + default "Chili base board" + +config VARIANT_DIR + string + default "base" if BOARD_SIEMENS_CHILI_BASE + +config DEVICETREE + string + default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" + +config INTEL_GMA_VBT_FILE + string + default "src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/data.vbt" + +config DIMM_SPD_SIZE + int + default 512 + +config CBFS_SIZE + hex + default 0xb00000 + +config POST_DEVICE + bool + default n + +endif diff --git a/src/mainboard/siemens/chili/Kconfig.name b/src/mainboard/siemens/chili/Kconfig.name new file mode 100644 index 0000000..a96a28c --- /dev/null +++ b/src/mainboard/siemens/chili/Kconfig.name @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0-only + +comment "CHILI" + +config BOARD_SIEMENS_CHILI_BASE + bool "-> Base board" diff --git a/src/mainboard/siemens/chili/Makefile.inc b/src/mainboard/siemens/chili/Makefile.inc new file mode 100644 index 0000000..abeedf3 --- /dev/null +++ b/src/mainboard/siemens/chili/Makefile.inc @@ -0,0 +1,12 @@ +## SPDX-License-Identifier: GPL-2.0-only + +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR) + +romstage-y += romstage.c + +ramstage-y += mainboard.c +ramstage-y += ec.c + +smm-y += ec.c + +subdirs-y += variants/$(VARIANT_DIR) diff --git a/src/mainboard/siemens/chili/board_info.txt b/src/mainboard/siemens/chili/board_info.txt new file mode 100644 index 0000000..cb5b428 --- /dev/null +++ b/src/mainboard/siemens/chili/board_info.txt @@ -0,0 +1,5 @@ +Vendor name: Siemens +Category: eval +ROM protocol: SPI +ROM socketed: n +Flashrom support: n diff --git a/src/mainboard/siemens/chili/cmos.layout b/src/mainboard/siemens/chili/cmos.layout new file mode 100644 index 0000000..4a758d9 --- /dev/null +++ b/src/mainboard/siemens/chili/cmos.layout @@ -0,0 +1,59 @@ +## SPDX-License-Identifier: GPL-2.0-only + +# ----------------------------------------------------------------- +entries + +#start-bit length config config-ID name + +0 120 r 0 reserved_memory + +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter + +# coreboot config options: console +395 4 e 3 debug_level + +# coreboot config options: cpu +400 1 e 2 hyper_threading +401 1 e 2 vtd + +# coreboot config options: pch +408 2 e 4 power_on_after_fail + +# coreboot config options: mainboard +440 1 e 2 ethernet1 + +# payload config options +512 256 s 0 boot_devices +768 8 h 0 boot_default +784 1 e 1 cmos_defaults_loaded + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 No +1 1 Yes +2 0 Disable +2 1 Enable +3 0 Emergency +3 1 Alert +3 2 Critical +3 3 Error +3 4 Warning +3 5 Notice +3 6 Info +3 7 Debug +3 8 Spew +4 0 Disable +4 1 Enable +4 2 Keep +# ----------------------------------------------------------------- +checksums + +checksum 392 983 984 diff --git a/src/mainboard/siemens/chili/dsdt.asl b/src/mainboard/siemens/chili/dsdt.asl new file mode 100644 index 0000000..6fd12b1 --- /dev/null +++ b/src/mainboard/siemens/chili/dsdt.asl @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 // OEM revision +) +{ + #include <soc/intel/common/block/acpi/acpi/platform.asl> + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> + + Device (_SB.PCI0) { + #include <soc/intel/common/block/acpi/acpi/northbridge.asl> + #include <soc/intel/cannonlake/acpi/southbridge.asl> + } + + #include <southbridge/intel/common/acpi/sleepstates.asl> +} diff --git a/src/mainboard/siemens/chili/ec.c b/src/mainboard/siemens/chili/ec.c new file mode 100644 index 0000000..bc0eb7d --- /dev/null +++ b/src/mainboard/siemens/chili/ec.c @@ -0,0 +1,99 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +#include <console/console.h> +#include <cpu/x86/smm.h> +#include <ec/acpi/ec.h> +#include <timer.h> + +#include "ec.h" + +#define EC_STATUS 0x50 +#define EC_RUNNING (1 << 1) +#define EC_DEVICE_CONTROL_1 0x80 +#define EC_DEVICE_CONTROL_1_PROGAS_ON (1 << 0) +#define EC_DEVICE_CONTROL_1_BOOMER_ON (1 << 1) +#define EC_DEVICE_CONTROL_1_BT_RF_ON (1 << 2) +#define EC_DEVICE_CONTROL_1_TP_ON (1 << 3) +#define EC_DEVICE_CONTROL_1_LAN2_RST (1 << 6) +#define EC_DEVICE_CONTROL_2 0x81 +#define EC_DEVICE_CONTROL_2_LAN_1_ON (1 << 0) +#define EC_DEVICE_CONTROL_2_LAN_2_ON (1 << 1) +#define EC_DEVICE_CONTROL_2_WLAN_ON (1 << 2) +#define EC_DEVICE_CONTROL_2_USB_ON (1 << 3) +#define EC_DEVICE_CONTROL_2_IDE1_ON (1 << 4) +#define EC_DEVICE_CONTROL_2_IDE2_ON (1 << 5) +#define EC_DEVICE_CONTROL_2_COM1_ON (1 << 6) +#define EC_DEVICE_CONTROL_2_MPI_ON (1 << 7) + +#define RUNNING_TIMEOUT_MS 3333 + +static bool ec_running(void) +{ + struct stopwatch sw; + uint8_t ec_status; + + stopwatch_init_msecs_expire(&sw, RUNNING_TIMEOUT_MS); + do + ec_status = ec_read(EC_STATUS); + while (!(ec_status & EC_RUNNING) && !stopwatch_expired(&sw)); + + if (!(ec_status & EC_RUNNING)) + printk(BIOS_WARNING, "EC not ready after %dms\n", RUNNING_TIMEOUT_MS); + + return !!(ec_status & EC_RUNNING); +} + +void ec_enable_devices(bool enable_usb) +{ + uint8_t control_1, control_2; + + if (!ec_running()) + return; + + control_1 = ec_read(EC_DEVICE_CONTROL_1); + control_2 = ec_read(EC_DEVICE_CONTROL_2); + + printk(BIOS_INFO, "EC previous EDC1: 0x%02x\n", control_1); + printk(BIOS_INFO, "EC previous EDC2: 0x%02x\n", control_2); + + control_1 &= ~(EC_DEVICE_CONTROL_1_BT_RF_ON); + control_1 |= EC_DEVICE_CONTROL_1_BOOMER_ON; + + control_2 &= ~(EC_DEVICE_CONTROL_2_WLAN_ON | EC_DEVICE_CONTROL_2_USB_ON); + control_2 |= EC_DEVICE_CONTROL_2_MPI_ON; + if (enable_usb) + control_2 |= EC_DEVICE_CONTROL_2_USB_ON; + + ec_write(EC_DEVICE_CONTROL_1, control_1); + ec_write(EC_DEVICE_CONTROL_2, control_2); + + printk(BIOS_INFO, "EC current EDC1: 0x%02x\n", ec_read(EC_DEVICE_CONTROL_1)); + printk(BIOS_INFO, "EC current EDC2: 0x%02x\n", ec_read(EC_DEVICE_CONTROL_2)); +} + +void mainboard_smi_sleep(const uint8_t slp_typ) +{ + uint8_t control_1, control_2; + + if (slp_typ != ACPI_S5) + return; + + if (!ec_running()) + return; + + control_1 = ec_read(EC_DEVICE_CONTROL_1); + control_2 = ec_read(EC_DEVICE_CONTROL_2); + + printk(BIOS_INFO, "EC previous EDC1: 0x%02x\n", control_1); + printk(BIOS_INFO, "EC previous EDC2: 0x%02x\n", control_2); + + control_1 &= ~(EC_DEVICE_CONTROL_1_BOOMER_ON); + control_2 &= ~(EC_DEVICE_CONTROL_2_USB_ON | EC_DEVICE_CONTROL_2_MPI_ON); + + ec_write(EC_DEVICE_CONTROL_1, control_1); + ec_write(EC_DEVICE_CONTROL_2, control_2); + + printk(BIOS_INFO, "EC current EDC1: 0x%02x\n", ec_read(EC_DEVICE_CONTROL_1)); + printk(BIOS_INFO, "EC current EDC2: 0x%02x\n", ec_read(EC_DEVICE_CONTROL_2)); +} diff --git a/src/mainboard/siemens/chili/ec.h b/src/mainboard/siemens/chili/ec.h new file mode 100644 index 0000000..50d724f --- /dev/null +++ b/src/mainboard/siemens/chili/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SIEMENS_CHILI_EC_H +#define _SIEMENS_CHILI_EC_H + +void ec_enable_devices(bool enable_usb); + +#endif /* _SIEMENS_CHILI_EC_H */ diff --git a/src/mainboard/siemens/chili/mainboard.c b/src/mainboard/siemens/chili/mainboard.c new file mode 100644 index 0000000..42e132d --- /dev/null +++ b/src/mainboard/siemens/chili/mainboard.c @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/device.h> + +#include "ec.h" + +static void mainboard_dev_init(struct device *dev) +{ + const bool enable_usb = CONFIG(BOARD_SIEMENS_CHILI_BASE); + ec_enable_devices(enable_usb); +} + +static void mainboard_enable(struct device *dev) +{ + dev->ops->init = mainboard_dev_init; +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/siemens/chili/romstage.c b/src/mainboard/siemens/chili/romstage.c new file mode 100644 index 0000000..9c941c2 --- /dev/null +++ b/src/mainboard/siemens/chili/romstage.c @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <option.h> +#include <soc/cnl_memcfg_init.h> +#include <soc/gpio.h> +#include <soc/romstage.h> + +#include "variant.h" + +static void mainboard_init(void) +{ + const struct pad_config *pads; + size_t num; + + pads = variant_gpio_table(&num); + gpio_configure_pads(pads, num); +} + +void mainboard_memory_init_params(FSPM_UPD *memupd) +{ + uint8_t vtd = 1; + const struct cnl_mb_cfg cfg = { + .spd = { + [0] = { READ_SMBUS, { 0x50 << 1 } }, + [2] = { READ_SMBUS, { 0x52 << 1 } }, + }, + .rcomp_resistor = { 121, 75, 100 }, + .rcomp_targets = { 50, 25, 20, 20, 26 }, + .dq_pins_interleaved = 1, + .vref_ca_config = 2, + .ect = 0, + }; + cannonlake_memcfg_init(&memupd->FspmConfig, &cfg); + memupd->FspmConfig.EccSupport = 1; + memupd->FspmConfig.UserBd = BOARD_TYPE_MOBILE; + + get_option(&vtd, "vtd"); + memupd->FspmTestConfig.VtdDisable = !vtd; + get_option(&memupd->FspmConfig.HyperThreading, "hyper_threading"); + + mainboard_init(); +} diff --git a/src/mainboard/siemens/chili/variant.h b/src/mainboard/siemens/chili/variant.h new file mode 100644 index 0000000..423608f --- /dev/null +++ b/src/mainboard/siemens/chili/variant.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _VARIANT_H_ +#define _VARIANT_H_ + +const struct pad_config *variant_gpio_table(size_t *num); + +#endif /* _VARIANT_H_ */ diff --git a/src/mainboard/siemens/chili/variants/base/Makefile.inc b/src/mainboard/siemens/chili/variants/base/Makefile.inc new file mode 100644 index 0000000..86b9433 --- /dev/null +++ b/src/mainboard/siemens/chili/variants/base/Makefile.inc @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-only + +romstage-y += gpio.c + +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/siemens/chili/variants/base/board_info.txt b/src/mainboard/siemens/chili/variants/base/board_info.txt new file mode 100644 index 0000000..a5d0991 --- /dev/null +++ b/src/mainboard/siemens/chili/variants/base/board_info.txt @@ -0,0 +1 @@ +Board name: Chili base board diff --git a/src/mainboard/siemens/chili/variants/base/data.vbt b/src/mainboard/siemens/chili/variants/base/data.vbt new file mode 100644 index 0000000..f79a6005 --- /dev/null +++ b/src/mainboard/siemens/chili/variants/base/data.vbt Binary files differ diff --git a/src/mainboard/siemens/chili/variants/base/devicetree.cb b/src/mainboard/siemens/chili/variants/base/devicetree.cb new file mode 100644 index 0000000..505e9a4 --- /dev/null +++ b/src/mainboard/siemens/chili/variants/base/devicetree.cb @@ -0,0 +1,136 @@ +# SPDX-License-Identifier: GPL-2.0-only + +chip soc/intel/cannonlake + # FSP configuration + register "SaGv" = "SaGv_Enabled" + register "RMT" = "0" + register "speed_shift_enable" = "1" + + register "PchHdaDspEnable" = "0" + register "PchHdaAudioLinkHda" = "1" + + device cpu_cluster 0 on + device lapic 0 on end + end + + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 01.0 off end # PCIe x16 + device pci 01.1 off end # PCIe x8 + device pci 01.2 off end # PCIe x4 + device pci 02.0 on end # Integrated Graphics Device + device pci 04.0 on end # SA Thermal device + device pci 05.0 off end # Imaging Processing Unit + device pci 08.0 off end # Gaussian mixture model, Neural network accelerator + device pci 12.0 on end # Thermal Subsystem + device pci 12.5 off end # UFS SCS + device pci 12.6 off end # GSPI #2 + device pci 13.0 off end # ISH + device pci 14.0 on # USB xHCI + # USB2 + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC2)" # Type-C? + register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" # single blue + register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # SIMATIC NET CP 5711 + register "usb2_ports[7]" = "USB2_PORT_MID(OC1)" # upper blue + register "usb2_ports[8]" = "USB2_PORT_MID(OC4)" # lower blue + register "usb2_ports[11]" = "USB2_PORT_MID(OC_SKIP)" # STM SC? + # USB3 + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # Type-C? + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # upper blue + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC4)" # lower blue + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Realtek storage? + register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)" # single blue + end + device pci 14.1 off end # USB xDCI (OTG) + device pci 14.2 on end # Shared SRAM + device pci 14.3 off end # CNVi Wifi + device pci 14.5 off end # SDCard + device pci 15.0 off end # I2C #0 + device pci 15.1 off end # I2C #1 + device pci 15.2 off end # I2C #2 + device pci 15.3 off end # I2C #3 + device pci 16.0 on # Management Engine Interface 1 + register "HeciEnabled" = "1" + end + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 16.5 off end # Management Engine Interface 4 + device pci 17.0 on # SATA + register "SataSalpSupport" = "1" + register "SataPortsEnable[0]" = "1" # HDD / SSD + register "SataPortsEnable[1]" = "1" # ODD + register "SataPortsEnable[3]" = "1" # HDD / SSD + + register "SataPortsDevSlp[0]" = "1" # M.2 + register "SataPortsDevSlp[2]" = "1" # HDD / SSD + end + device pci 19.0 off end # I2C #4 + device pci 19.1 off end # I2C #5 + device pci 19.2 off end # UART #2 + device pci 1a.0 off end # eMMC + device pci 1c.0 off end # PCI Express Port 1 + device pci 1c.1 off end # PCI Express Port 2 + device pci 1c.2 off end # PCI Express Port 3 + device pci 1c.3 off end # PCI Express Port 4 + device pci 1c.4 on # PCI Express Port 5 + device pci 00.0 on end # x1 i219 + register "PcieRpEnable[4]" = "1" + register "PcieClkSrcUsage[4]" = "0x70" + register "PcieClkSrcClkReq[4]" = "4" + register "PcieRpSlotImplemented[4]" = "0" + end + device pci 1c.5 on # PCI Express Port 6 + device pci 00.0 on end # x1 i210 + register "PcieRpEnable[5]" = "1" + register "PcieClkSrcUsage[5]" = "5" + register "PcieClkSrcClkReq[5]" = "5" + register "PcieRpSlotImplemented[5]" = "0" + end + device pci 1c.6 on # PCI Express Port 7 + device pci 00.0 on end # x1 M.2 (WLAN / BT) + register "PcieRpEnable[6]" = "1" + register "PcieRpSlotImplemented[6]" = "1" + end + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 off end # PCI Express Port 9 + device pci 1d.1 off end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1d.4 off end # PCI Express Port 13 + device pci 1d.5 off end # PCI Express Port 14 + device pci 1d.6 off end # PCI Express Port 15 + device pci 1d.7 off end # PCI Express Port 16 + device pci 1b.0 on # PCI Express Port 17 + device pci 00.0 on end # x4 M.2/M + register "PcieRpEnable[16]" = "1" + register "PcieClkSrcUsage[7]" = "16" + register "PcieClkSrcClkReq[7]" = "7" + register "PcieRpSlotImplemented[16]" = "1" + end + device pci 1b.1 off end # PCI Express Port 18 + device pci 1b.2 off end # PCI Express Port 19 + device pci 1b.3 off end # PCI Express Port 20 + device pci 1b.4 off end # PCI Express Port 21 + device pci 1b.5 off end # PCI Express Port 22 + device pci 1b.6 off end # PCI Express Port 23 + device pci 1b.7 off end # PCI Express Port 24 + device pci 1e.0 off end # UART #0 + device pci 1e.1 off end # UART #1 + device pci 1e.2 off end # GSPI #0 + device pci 1e.3 off end # GSPI #1 + device pci 1f.0 on # LPC Interface + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + end + device pci 1f.1 on end # P2SB + device pci 1f.2 on end # Power Management Controller + device pci 1f.3 on end # Intel HDA + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # PCH SPI + device pci 1f.6 on end # GbE + device pci 1f.7 off end # TraceHub + end +end diff --git a/src/mainboard/siemens/chili/variants/base/gma-mainboard.ads b/src/mainboard/siemens/chili/variants/base/gma-mainboard.ads new file mode 100644 index 0000000..42a2f2c --- /dev/null +++ b/src/mainboard/siemens/chili/variants/base/gma-mainboard.ads @@ -0,0 +1,19 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP1, -- VGA (DVI-I) + HDMI2, -- DVI-I + DP3, -- DP++ + HDMI3, -- DP++ + eDP, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/siemens/chili/variants/base/gpio.c b/src/mainboard/siemens/chili/variants/base/gpio.c new file mode 100644 index 0000000..65ea037 --- /dev/null +++ b/src/mainboard/siemens/chili/variants/base/gpio.c @@ -0,0 +1,129 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/gpio.h> +#include "variant.h" + +static const struct pad_config gpio_table[] = { +/* GPP_A14 GPIO */ PAD_NC(GPP_A14, NONE), +/* GPP_A16 GPIO */ PAD_NC(GPP_A16, DN_20K), +/* GPP_B4 GPIO */ PAD_CFG_GPO(GPP_B4, 0, DEEP), +/* GPP_B5 GPIO */ PAD_NC(GPP_B5, NONE), +/* GPP_B6 GPIO */ PAD_NC(GPP_B6, NONE), +/* GPP_B8 GPIO */ PAD_NC(GPP_B8, NONE), +/* GPP_B10 GPIO */ PAD_NC(GPP_B10, NONE), +/* GPP_B11 GPIO */ PAD_CFG_GPO(GPP_B11, 1, DEEP), +/* GPP_B14 SPKR */ PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), +/* GPP_B18 GPIO */ PAD_NC(GPP_B18, NONE), +/* GPP_B22 GPIO */ PAD_NC(GPP_B22, NONE), +/* GPP_C2 GPIO */ PAD_NC(GPP_C2, NONE), +/* GPP_C5 GPIO */ PAD_NC(GPP_C5, NONE), +/* GPP_C6 SML1CLK */ PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), +/* GPP_C7 SML1DATA */ PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), +/* GPP_C8 GPIO */ PAD_NC(GPP_C8, NONE), +/* GPP_C9 GPIO */ PAD_NC(GPP_C9, NONE), +/* GPP_C12 GPIO */ PAD_CFG_GPI(GPP_C12, NONE, DEEP), +/* GPP_C13 GPIO */ PAD_CFG_GPI(GPP_C13, NONE, DEEP), +/* GPP_C14 GPIO */ PAD_CFG_GPI(GPP_C14, NONE, DEEP), +/* GPP_C15 GPIO */ PAD_CFG_GPI(GPP_C15, NONE, DEEP), +/* GPP_C16 I2C0_SDA */ PAD_CFG_NF(GPP_C16, NONE, PLTRST, NF1), +/* GPP_C17 I2C0_SCL */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), +/* GPP_C20 UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), +/* GPP_C21 UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), +/* GPP_C22 UART2_RTS# */ PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1), +/* GPP_C23 UART2_CTS# */ PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1), +/* GPP_D1 GPIO */ PAD_CFG_GPI(GPP_D1, NONE, DEEP), +/* GPP_D2 GPIO */ PAD_CFG_GPI(GPP_D2, NONE, DEEP), +/* GPP_D3 GPIO */ PAD_CFG_GPO(GPP_D3, 1, DEEP), +/* GPP_D7 GPIO */ PAD_CFG_GPI(GPP_D7, NONE, PLTRST), +/* GPP_D8 GPIO */ PAD_CFG_GPI(GPP_D8, NONE, PLTRST), +/* GPP_D17 DMIC_CLK1 */ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), +/* GPP_D18 DMIC_DATA1 */ PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), +/* GPP_D19 DMIC_CLK0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), +/* GPP_D20 DMIC_DATA0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), +/* GPP_D21 GPIO */ PAD_CFG_GPO(GPP_D21, 1, DEEP), +/* GPP_D22 GPIO */ PAD_CFG_GPI(GPP_D22, NONE, DEEP), +/* GPP_G1 GPIO */ PAD_CFG_GPO(GPP_G1, 1, PLTRST), +/* GPP_G2 GPIO */ PAD_CFG_GPI(GPP_G2, NONE, PLTRST), +/* GPP_G3 GPIO */ PAD_CFG_GPI_APIC(GPP_G3, NONE, DEEP, LEVEL, INVERT), +/* I2S1_SFRM GPIO */ PAD_NC(I2S1_SFRM, NONE), +/* I2S1_TXD GPIO */ PAD_NC(I2S1_TXD, NONE), +/* GPD0 BATLOW# */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), +/* GPD1 ACPRESENT */ PAD_CFG_NF(GPD1, NATIVE, DEEP, NF1), +/* GPD7 GPIO */ PAD_CFG_GPO(GPD7, 0, RSMRST), +/* GPP_K0 GPIO */ PAD_CFG_GPI(GPP_K0, NONE, PLTRST), +/* GPP_K1 GPIO */ PAD_CFG_GPI(GPP_K1, NONE, PLTRST), +/* GPP_K2 GPIO */ PAD_CFG_GPI(GPP_K2, NONE, PLTRST), +/* GPP_K3 GPIO */ PAD_CFG_GPI(GPP_K3, NONE, PLTRST), +/* GPP_K4 GPIO */ PAD_CFG_GPO(GPP_K4, 1, PWROK), +/* GPP_K5 GPIO */ PAD_CFG_GPO(GPP_K5, 1, PWROK), +/* GPP_K8 GPIO */ PAD_NC(GPP_K8, NONE), +/* GPP_K9 GPIO */ PAD_NC(GPP_K9, NONE), +/* GPP_K10 GPIO */ PAD_NC(GPP_K10, NONE), +/* GPP_K11 GPIO */ PAD_NC(GPP_K11, NONE), +/* GPP_K20 GPIO */ PAD_CFG_GPO(GPP_K20, 1, PLTRST), +/* GPP_K21 GPIO */ PAD_NC(GPP_K21, NONE), +/* GPP_H0 GPIO */ PAD_CFG_GPI(GPP_H0, NONE, PLTRST), +/* GPP_H2 GPIO */ PAD_NC(GPP_H2, NONE), +/* GPP_H3 GPIO */ PAD_NC(GPP_H3, NONE), +/* GPP_H10 GPIO */ PAD_CFG_GPI(GPP_H10, NONE, DEEP), +/* GPP_H15 GPIO */ PAD_CFG_GPO(GPP_H15, 1, DEEP), +/* GPP_H17 GPIO */ PAD_CFG_GPO(GPP_H17, 1, DEEP), +/* GPP_E0 SATAXPCIE0 */ PAD_CFG_NF(GPP_E0, NONE, DEEP, NF1), +/* GPP_E1 GPIO */ PAD_NC(GPP_E1, NONE), +/* GPP_E2 GPIO */ PAD_NC(GPP_E2, NONE), +/* GPP_E4 SATA_DEVSLP0 */ PAD_CFG_NF(GPP_E4, NONE, DEEP, NF1), +/* GPP_E5 GPIO */ PAD_CFG_GPI(GPP_E5, NONE, DEEP), +/* GPP_E6 GPIO */ PAD_CFG_GPI(GPP_E6, NONE, DEEP), +/* GPP_E8 SATALED# */ PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), +/* GPP_E9 USB2_OC0# */ PAD_CFG_NF(GPP_E9, UP_20K, DEEP, NF1), +/* GPP_E10 USB2_OC1# */ PAD_CFG_NF(GPP_E10, UP_20K, DEEP, NF1), +/* GPP_E11 USB2_OC2# */ PAD_CFG_NF(GPP_E11, UP_20K, DEEP, NF1), +/* GPP_E12 GPIO */ PAD_CFG_GPO(GPP_E12, 1, PLTRST), +/* GPP_F1 GPIO */ PAD_NC(GPP_F1, NONE), +/* GPP_F2 GPIO */ PAD_NC(GPP_F2, NONE), +/* GPP_F3 GPIO */ PAD_NC(GPP_F3, NONE), +/* GPP_F4 GPIO */ PAD_NC(GPP_F4, NONE), +/* GPP_F5 GPIO */ PAD_CFG_GPO(GPP_F5, 1, PLTRST), +/* GPP_F6 SATA_DEVSLP4 */ PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), +/* GPP_F8 GPIO */ PAD_CFG_GPO(GPP_F8, 0, DEEP), +/* GPP_F9 GPIO */ PAD_CFG_GPO(GPP_F9, 0, DEEP), +/* GPP_F10 GPIO */ PAD_CFG_GPI(GPP_F10, NONE, PLTRST), +/* GPP_F13 GPIO */ PAD_CFG_GPI(GPP_F13, NONE, PLTRST), +/* GPP_F14 GPIO */ PAD_NC(GPP_F14, NONE), +/* GPP_F15 USB2_OC4# */ PAD_CFG_NF(GPP_F15, UP_20K, DEEP, NF1), +/* GPP_F16 USB2_OC5# */ PAD_CFG_NF(GPP_F16, UP_20K, DEEP, NF1), +/* GPP_F17 USB2_OC6# */ PAD_CFG_NF(GPP_F17, UP_20K, DEEP, NF1), +/* GPP_F18 GPIO */ PAD_CFG_GPI_APIC(GPP_F18, NONE, DEEP, LEVEL, INVERT), +/* GPP_F19 eDP_VDDEN */ PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), +/* GPP_F20 eDP_BKLTEN */ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), +/* GPP_F21 eDP_BKLTCTL */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), +/* GPP_F22 DDPF_CTRLCLK */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), +/* GPP_F23 DDPF_CTRLDATA */ PAD_CFG_NF(GPP_F23, NONE, DEEP, NF1), +/* GPP_I0 DDPB_HPD0 */ PAD_CFG_NF(GPP_I0, NATIVE, DEEP, NF1), +/* GPP_I1 DDPB_HPD1 */ PAD_CFG_NF(GPP_I1, NATIVE, DEEP, NF1), +/* GPP_I2 DDPB_HPD2 */ PAD_CFG_NF(GPP_I2, NATIVE, DEEP, NF1), +/* GPP_I3 DDPB_HPD3 */ PAD_CFG_NF(GPP_I3, NONE, DEEP, NF1), +/* GPP_I4 EDP_HPD */ PAD_CFG_NF(GPP_I4, NONE, DEEP, NF1), +/* GPP_I5 DDPB_CTRLCLK */ PAD_CFG_NF(GPP_I5, NONE, DEEP, NF1), +/* GPP_I6 DDPB_CTRLDATA */ PAD_CFG_NF(GPP_I6, NONE, DEEP, NF1), +/* GPP_I7 DDPC_CTRLCLK */ PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1), +/* GPP_I8 DDPC_CTRLDATA */ PAD_CFG_NF(GPP_I8, NONE, DEEP, NF1), +/* GPP_I9 DDPD_CTRLCLK */ PAD_CFG_NF(GPP_I9, DN_20K, DEEP, NF1), +/* GPP_I10 DDPD_CTRLDATA */ PAD_CFG_NF(GPP_I10, DN_20K, DEEP, NF1), +/* GPP_J2 n/a */ PAD_CFG_NF(GPP_J2, NONE, DEEP, NF1), +/* GPP_J3 n/a */ PAD_CFG_NF(GPP_J3, NONE, DEEP, NF1), +/* GPP_J4 CNV_BRI_DT */ PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1), +/* GPP_J5 CNV_BRI_RSP */ PAD_CFG_NF(GPP_J5, NONE, DEEP, NF1), +/* GPP_J6 CNV_RGI_DT */ PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1), +/* GPP_J7 CNV_RGI_RSP */ PAD_CFG_NF(GPP_J7, NONE, DEEP, NF1), +/* GPP_J8 CNV_MFUART2_RXD */ PAD_CFG_NF(GPP_J8, NONE, DEEP, NF1), +/* GPP_J9 CNV_MFUART2_TXD */ PAD_CFG_NF(GPP_J9, NONE, DEEP, NF1), +/* GPP_J10 n/a */ PAD_CFG_NF(GPP_J10, NONE, DEEP, NF1), +/* GPP_J11 A4WP_PRESENT */ PAD_CFG_NF(GPP_J11, NONE, DEEP, NF1), +}; + +const struct pad_config *variant_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +}
Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39976 )
Change subject: mb/siemens/chili: Add new mainboard ......................................................................
Patch Set 40:
Ah, sorry for not responding. I didn't realize that you commented last week.
However, everything works :)
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Angel Pons (Code Review) -
build bot (Jenkins) (Code Review)
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Felix Singer (Code Review)
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HAOUAS Elyes (Code Review)
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Nico Huber (Code Review)
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Patrick Georgi (Code Review)
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Paul Menzel (Code Review)
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Sebastian Witt (Code Review)