Change in coreboot[master]: cpu/intel/smm: Make sure SMRR base is aligned to SMRR size

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/27870

Change subject: cpu/intel/smm: Make sure SMRR base is aligned to SMRR size
......................................................................

cpu/intel/smm: Make sure SMRR base is aligned to SMRR size

If TSEG_BASE is not TSEG_SIZE aligned the SMRR settings are invalid, therefore
guard against this.

Change-Id: I48f55cdac5f4b16b9a8d7a8ef3a84918e756e315
Signed-off-by: Arthur Heymans 
---
M src/cpu/intel/smm/gen1/smmrelocate.c
1 file changed, 19 insertions(+), 13 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/27870/1

diff --git a/src/cpu/intel/smm/gen1/smmrelocate.c b/src/cpu/intel/smm/gen1/smmrelocate.c
index b48fe00..a298985 100644
--- a/src/cpu/intel/smm/gen1/smmrelocate.c
+++ b/src/cpu/intel/smm/gen1/smmrelocate.c
@@ -160,20 +160,26 @@
    if (IS_ENABLED(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM))
    	params->smram_size -= CONFIG_SMM_RESERVED_SIZE;

-	/* SMRR has 32-bits of valid address aligned to 4KiB. */
-	struct cpuinfo_x86 c;
+	if (IS_ALIGNED(tsegmb, tseg_size)) {
+		/* SMRR has 32-bits of valid address aligned to 4KiB. */
+		struct cpuinfo_x86 c;

-	/* On model_6fx and model_1067x bits [0:11] on smrr_base are reserved */
-	get_fms(&c, cpuid_eax(1));
-	if (c.x86 == 6 && (c.x86_model == 0xf || c.x86_model == 0x17))
-		params->smrr_base.lo = (params->smram_base & rmask);
-	else
-		params->smrr_base.lo = (params->smram_base & rmask)
-			| MTRR_TYPE_WRBACK;
-	params->smrr_base.hi = 0;
-	params->smrr_mask.lo = (~(tseg_size - 1) & rmask)
-		| MTRR_PHYS_MASK_VALID;
-	params->smrr_mask.hi = 0;
+		/* On model_6fx and model_1067x bits [0:11] on smrr_base
+		   are reserved */
+		get_fms(&c, cpuid_eax(1));
+		if (c.x86 == 6 && (c.x86_model == 0xf || c.x86_model == 0x17))
+			params->smrr_base.lo = (params->smram_base & rmask);
+		else
+			params->smrr_base.lo = (params->smram_base & rmask)
+				| MTRR_TYPE_WRBACK;
+		params->smrr_base.hi = 0;
+		params->smrr_mask.lo = (~((1 << 20) - 1) & rmask)
+			| MTRR_PHYS_MASK_VALID;
+		params->smrr_mask.hi = 0;
+	} else {
+		printk(BIOS_WARNING,
+		       "TSEG base not aligned with TSEG SIZE! Not setting SMRR\n");
+	}
 }

static int install_relocation_handler(int *apic_id_map, int num_cpus,