Change in coreboot[master]: mb/google/brya: Enable HECI1 communication

[Sridhar Siricilla (Code Review)]

Sridhar Siricilla has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/54210 )

Change subject: mb/google/brya: Enable HECI1 communication
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mb/google/brya: Enable HECI1 communication

The patch enables HECI1 interface to allow OS applications to communicate
with CSE.

TEST=Verify PCI device 0:16.0 exposed in the lspci output

Signed-off-by: Sridhar Siricilla 
Change-Id: I73acdd99788f9b60b7bcea372145e9694a124174
---
M src/mainboard/google/brya/variants/baseboard/devicetree.cb
1 file changed, 3 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/54210/1

diff --git a/src/mainboard/google/brya/variants/baseboard/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/devicetree.cb
index e7a6ed3..4097ab6 100644
--- a/src/mainboard/google/brya/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/brya/variants/baseboard/devicetree.cb
@@ -17,6 +17,9 @@
         # S0ix enable
         register "s0ix_enable" = "1"

+	# Enable heci communication
+	register "HeciEnabled" = "1"
+
    # This disabled autonomous GPIO power management, otherwise
    # old cr50 FW only supports short pulses; need to clarify
    # the minimum PCH IRQ pulse width with Intel, b/180111628