Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46373 )
Change subject: haswell/broadwell: Fix `BLCK` typo ......................................................................
haswell/broadwell: Fix `BLCK` typo
Change-Id: Ifed3c8250d5c9869493285d0b87580b70ff37965 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/cpu/intel/haswell/haswell_init.c M src/soc/intel/broadwell/cpu.c 2 files changed, 8 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/46373/1
diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index ac5dec6..d08f251 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -207,8 +207,8 @@ return ult; }
-/* The core 100MHz BLCK is disabled in deeper c-states. One needs to calibrate - * the 100MHz BCLCK against the 24MHz BLCK to restore the clocks properly +/* The core 100MHz BCLK is disabled in deeper c-states. One needs to calibrate + * the 100MHz BCLCK against the 24MHz BCLK to restore the clocks properly * when a core is woken up. */ static int pcode_ready(void) { @@ -247,7 +247,7 @@
err_code = MCHBAR32(BIOS_MAILBOX_INTERFACE) & 0xff;
- printk(BIOS_DEBUG, "PCODE: 24MHz BLCK calibration response: %d\n", + printk(BIOS_DEBUG, "PCODE: 24MHz BCLK calibration response: %d\n", err_code);
/* Read the calibrated value. */ @@ -259,7 +259,7 @@ return; }
- printk(BIOS_DEBUG, "PCODE: 24MHz BLCK calibration value: 0x%08x\n", + printk(BIOS_DEBUG, "PCODE: 24MHz BCLK calibration value: 0x%08x\n", MCHBAR32(BIOS_MAILBOX_DATA)); }
diff --git a/src/soc/intel/broadwell/cpu.c b/src/soc/intel/broadwell/cpu.c index c64af02..e866136 100644 --- a/src/soc/intel/broadwell/cpu.c +++ b/src/soc/intel/broadwell/cpu.c @@ -25,8 +25,8 @@ #include <soc/intel/broadwell/chip.h> #include <cpu/intel/common/common.h>
-/* The core 100MHz BLCK is disabled in deeper c-states. One needs to calibrate - * the 100MHz BCLCK against the 24MHz BLCK to restore the clocks properly +/* The core 100MHz BCLK is disabled in deeper c-states. One needs to calibrate + * the 100MHz BCLCK against the 24MHz BCLK to restore the clocks properly * when a core is woken up. */ static int pcode_ready(void) { @@ -65,7 +65,7 @@
err_code = MCHBAR32(BIOS_MAILBOX_INTERFACE) & 0xff;
- printk(BIOS_DEBUG, "PCODE: 24MHz BLCK calibration response: %d\n", + printk(BIOS_DEBUG, "PCODE: 24MHz BCLK calibration response: %d\n", err_code);
/* Read the calibrated value. */ @@ -77,7 +77,7 @@ return; }
- printk(BIOS_DEBUG, "PCODE: 24MHz BLCK calibration value: 0x%08x\n", + printk(BIOS_DEBUG, "PCODE: 24MHz BCLK calibration value: 0x%08x\n", MCHBAR32(BIOS_MAILBOX_DATA)); }
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46373 )
Change subject: haswell/broadwell: Fix `BLCK` typo ......................................................................
Patch Set 2:
(2 comments)
https://review.coreboot.org/c/coreboot/+/46373/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/46373/2//COMMIT_MSG@7 PS2, Line 7: BLCK Probably better to use the correct spelling here.
https://review.coreboot.org/c/coreboot/+/46373/2/src/cpu/intel/haswell/haswe... File src/cpu/intel/haswell/haswell_init.c:
https://review.coreboot.org/c/coreboot/+/46373/2/src/cpu/intel/haswell/haswe... PS2, Line 211: * the 100MHz BCLCK against the 24MHz BCLK to restore the clocks properly Ugh, sorry, I thought this would be a quick review. But I don't understand the sentence at all and can't say if BCLK is meant here. I'll try to find something about this in the docs. 24MHz sounds like the usual external crystal btw.
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46373 )
Change subject: haswell/broadwell: Fix `BLCK` typo ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/46373/2/src/cpu/intel/haswell/haswe... File src/cpu/intel/haswell/haswell_init.c:
https://review.coreboot.org/c/coreboot/+/46373/2/src/cpu/intel/haswell/haswe... PS2, Line 211: * the 100MHz BCLCK against the 24MHz BCLK to restore the clocks properly
Ugh, sorry, I thought this would be a quick review. But I don't understand […]
Ok, they call them both BCLK. But that also includes that `BCLCK`. Please fix that too.
If you want, you can also align the /* style with our guidelines.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46373 )
Change subject: haswell/broadwell: Fix `BLCK` typo ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/46373/2/src/cpu/intel/haswell/haswe... File src/cpu/intel/haswell/haswell_init.c:
https://review.coreboot.org/c/coreboot/+/46373/2/src/cpu/intel/haswell/haswe... PS2, Line 211: * the 100MHz BCLCK against the 24MHz BCLK to restore the clocks properly
Ok, they call them both BCLK. But that also includes that `BCLCK`. Please […]
Oh, good catch.
Hello build bot (Jenkins), Nico Huber, Tim Wawrzynczak, Paul Menzel, Arthur Heymans, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46373
to look at the new patch set (#4).
Change subject: haswell/broadwell: Fix typos of `BCLK` ......................................................................
haswell/broadwell: Fix typos of `BCLK`
Change-Id: Ifed3c8250d5c9869493285d0b87580b70ff37965 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/cpu/intel/haswell/haswell_init.c M src/soc/intel/broadwell/cpu.c 2 files changed, 8 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/46373/4
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46373 )
Change subject: haswell/broadwell: Fix typos of `BCLK` ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/46373/2/src/cpu/intel/haswell/haswe... File src/cpu/intel/haswell/haswell_init.c:
https://review.coreboot.org/c/coreboot/+/46373/2/src/cpu/intel/haswell/haswe... PS2, Line 211: * the 100MHz BCLCK against the 24MHz BCLK to restore the clocks properly
Oh, good catch.
Done. Both Haswell and Broadwell are equally wrong w.r.t. comment style, so I'll fix that just once later
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46373 )
Change subject: haswell/broadwell: Fix typos of `BCLK` ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/46373/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/46373/2//COMMIT_MSG@7 PS2, Line 7: BLCK
Probably better to use the correct spelling here.
Good point, especially when there's two typo variants. Done.
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46373 )
Change subject: haswell/broadwell: Fix typos of `BCLK` ......................................................................
Patch Set 4: Code-Review+2
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46373 )
Change subject: haswell/broadwell: Fix typos of `BCLK` ......................................................................
Patch Set 4: Code-Review+1
Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46373 )
Change subject: haswell/broadwell: Fix typos of `BCLK` ......................................................................
Patch Set 4: Code-Review+2
Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46373 )
Change subject: haswell/broadwell: Fix typos of `BCLK` ......................................................................
haswell/broadwell: Fix typos of `BCLK`
Change-Id: Ifed3c8250d5c9869493285d0b87580b70ff37965 Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/46373 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Nico Huber nico.h@gmx.de Reviewed-by: Paul Menzel paulepanter@users.sourceforge.net Reviewed-by: Felix Singer felixsinger@posteo.net --- M src/cpu/intel/haswell/haswell_init.c M src/soc/intel/broadwell/cpu.c 2 files changed, 8 insertions(+), 8 deletions(-)
Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved Paul Menzel: Looks good to me, but someone else must approve Felix Singer: Looks good to me, approved
diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index ac5dec6..e03d30f 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -207,8 +207,8 @@ return ult; }
-/* The core 100MHz BLCK is disabled in deeper c-states. One needs to calibrate - * the 100MHz BCLCK against the 24MHz BLCK to restore the clocks properly +/* The core 100MHz BCLK is disabled in deeper c-states. One needs to calibrate + * the 100MHz BCLK against the 24MHz BCLK to restore the clocks properly * when a core is woken up. */ static int pcode_ready(void) { @@ -247,7 +247,7 @@
err_code = MCHBAR32(BIOS_MAILBOX_INTERFACE) & 0xff;
- printk(BIOS_DEBUG, "PCODE: 24MHz BLCK calibration response: %d\n", + printk(BIOS_DEBUG, "PCODE: 24MHz BCLK calibration response: %d\n", err_code);
/* Read the calibrated value. */ @@ -259,7 +259,7 @@ return; }
- printk(BIOS_DEBUG, "PCODE: 24MHz BLCK calibration value: 0x%08x\n", + printk(BIOS_DEBUG, "PCODE: 24MHz BCLK calibration value: 0x%08x\n", MCHBAR32(BIOS_MAILBOX_DATA)); }
diff --git a/src/soc/intel/broadwell/cpu.c b/src/soc/intel/broadwell/cpu.c index c64af02..179cd43 100644 --- a/src/soc/intel/broadwell/cpu.c +++ b/src/soc/intel/broadwell/cpu.c @@ -25,8 +25,8 @@ #include <soc/intel/broadwell/chip.h> #include <cpu/intel/common/common.h>
-/* The core 100MHz BLCK is disabled in deeper c-states. One needs to calibrate - * the 100MHz BCLCK against the 24MHz BLCK to restore the clocks properly +/* The core 100MHz BCLK is disabled in deeper c-states. One needs to calibrate + * the 100MHz BCLK against the 24MHz BCLK to restore the clocks properly * when a core is woken up. */ static int pcode_ready(void) { @@ -65,7 +65,7 @@
err_code = MCHBAR32(BIOS_MAILBOX_INTERFACE) & 0xff;
- printk(BIOS_DEBUG, "PCODE: 24MHz BLCK calibration response: %d\n", + printk(BIOS_DEBUG, "PCODE: 24MHz BCLK calibration response: %d\n", err_code);
/* Read the calibrated value. */ @@ -77,7 +77,7 @@ return; }
- printk(BIOS_DEBUG, "PCODE: 24MHz BLCK calibration value: 0x%08x\n", + printk(BIOS_DEBUG, "PCODE: 24MHz BCLK calibration value: 0x%08x\n", MCHBAR32(BIOS_MAILBOX_DATA)); }
-
Angel Pons (Code Review) -
Felix Singer (Code Review)
-
Nico Huber (Code Review)
-
Paul Menzel (Code Review)