Patch merged into coreboot/master: nb/amd/mct_ddr3: Fix RDIMM training on certain DIMMs

the following patch was just integrated into master:
commit 490160140af90f8d07ba897fed161c4c2599303b
Author: Timothy Pearson 
Date:   Wed Apr 20 14:00:39 2016 -0500

nb/amd/mct_ddr3: Fix RDIMM training on certain DIMMs

Certain RDIMMs have inherently large write levelling delays,
    in some cases exceeding 1.5 MEMCLK.  When these DIMMs are
    utilized, the phase recovery system requires special handling
    due to the resultant offset exceeding the phase recovery reporting
    capabilities.

Fix an old error where delays > 1.5 MEMCLK were not being programmed
    (gross delay high bit was not in set range), and restore special
    delay handling for delays greater than 1.5 MEMCLK.

Also enhance debugging for x4 DIMMs around the affected code.

Tested-On: ASUS KGPE-D16
    Config-CPU: 1x Opteron 6262HE
    Config-RAM: 4x Crucial 36KSF1G72PZ-1G6M1
    Change-Id: I0fb5454c4d5a9f308cc735597607f095fe9188db
    Signed-off-by: Timothy Pearson 
    Reviewed-on: https://review.coreboot.org/14441
    Tested-by: Raptor Engineering Automated Test Stand 
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth

See https://review.coreboot.org/14441 for details.

-gerrit