Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37980 )
Change subject: mb/amd/lamar: Switch away from ROMCC_BOOTBLOCK ......................................................................
mb/amd/lamar: Switch away from ROMCC_BOOTBLOCK
Warning: not tested on hardware.
Signed-off-by: Mike Banon mikebdp2@gmail.com Change-Id: I88fbe85401c8f627d0632a627cb4724db0526576 --- M src/mainboard/amd/lamar/Kconfig M src/mainboard/amd/lamar/Kconfig.name M src/mainboard/amd/lamar/Makefile.inc A src/mainboard/amd/lamar/bootblock.c D src/mainboard/amd/lamar/romstage.c 5 files changed, 48 insertions(+), 64 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/37980/1
diff --git a/src/mainboard/amd/lamar/Kconfig b/src/mainboard/amd/lamar/Kconfig index c856534..4915c03 100644 --- a/src/mainboard/amd/lamar/Kconfig +++ b/src/mainboard/amd/lamar/Kconfig @@ -13,15 +13,11 @@ # GNU General Public License for more details. #
-config BOARD_AMD_LAMAR - def_bool n - if BOARD_AMD_LAMAR
config BOARD_SPECIFIC_OPTIONS def_bool y #select BINARYPI_LEGACY_WRAPPER - #select ROMCC_BOOTBLOCK select CPU_AMD_PI_00630F01 select NORTHBRIDGE_AMD_PI_00630F01 select SOUTHBRIDGE_AMD_PI_BOLTON diff --git a/src/mainboard/amd/lamar/Kconfig.name b/src/mainboard/amd/lamar/Kconfig.name index 75eec04..1831b9a 100644 --- a/src/mainboard/amd/lamar/Kconfig.name +++ b/src/mainboard/amd/lamar/Kconfig.name @@ -1,3 +1,2 @@ -# Disabled -#config BOARD_AMD_LAMAR -# bool "Lamar" +config BOARD_AMD_LAMAR + bool "Lamar" diff --git a/src/mainboard/amd/lamar/Makefile.inc b/src/mainboard/amd/lamar/Makefile.inc index 37c1dce..e6934b4 100644 --- a/src/mainboard/amd/lamar/Makefile.inc +++ b/src/mainboard/amd/lamar/Makefile.inc @@ -13,6 +13,8 @@ # GNU General Public License for more details. #
+bootblock-y += bootblock.c + romstage-y += BiosCallOuts.c romstage-y += OemCustomize.c
diff --git a/src/mainboard/amd/lamar/bootblock.c b/src/mainboard/amd/lamar/bootblock.c new file mode 100644 index 0000000..45d19b4 --- /dev/null +++ b/src/mainboard/amd/lamar/bootblock.c @@ -0,0 +1,44 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <amdblocks/acpimmio.h> +#include <bootblock_common.h> +#include <superio/fintek/common/fintek.h> +#include <superio/fintek/f81216h/f81216h.h> + +#define SERIAL_DEV PNP_DEV(0x4e, F81216H_SP1) + +#define SB_MMIO_MISC32(x) *(volatile u32 *)(AMD_SB_ACPI_MMIO_ADDR + 0xE00 + (x)) + +static void sbxxx_enable_24mhzout(void) +{ + /* programming to 24MHz out signal */ + u32 reg32; + reg32 = SB_MMIO_MISC32(0x28); + reg32 |= 0x00040000; + SB_MMIO_MISC32(0x28) = reg32; + + reg32 = SB_MMIO_MISC32(0x40); + reg32 &= ~0x04u; + SB_MMIO_MISC32(0x40) = reg32; +} + +void bootblock_mainboard_early_init(void) +{ + u32 val; + + /* enable SIO clock */ + sbxxx_enable_24mhzout(); + + f81216h_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE, MODE_7777); +} diff --git a/src/mainboard/amd/lamar/romstage.c b/src/mainboard/amd/lamar/romstage.c deleted file mode 100644 index a22b247..0000000 --- a/src/mainboard/amd/lamar/romstage.c +++ /dev/null @@ -1,57 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 - 2014 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <device/pci_def.h> -#include <arch/io.h> -#include <arch/cpu.h> -#include <cpu/x86/lapic.h> -#include <console/console.h> -#include <northbridge/amd/agesa/state_machine.h> -#include <southbridge/amd/common/amd_defs.h> -#include <southbridge/amd/pi/hudson/hudson.h> -#include <superio/fintek/f81216h/f81216h.h> - -#define SERIAL_DEV PNP_DEV(0x4e, F81216H_SP1) - -static void romstage_main_template(void) -{ - u32 val; - - /* - * In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for - * LpcClk[1:0]". This following register setting has been - * replicated in every reference design since Parmer, so it is - * believed to be required even though it is not documented in - * the SoC BKDGs. Without this setting, there is no serial - * output. - */ - outb(0xD2, 0xcd6); - outb(0x00, 0xcd7); - - hudson_lpc_decode(); - - outb(0x24, 0xCD6); - outb(0x01, 0xCD7); - *(volatile u32 *) (AMD_SB_ACPI_MMIO_ADDR + 0xE00 + 0x28) |= 1 << 18; /* 24Mhz */ - *(volatile u32 *) (AMD_SB_ACPI_MMIO_ADDR + 0xE00 + 0x40) &= ~(1 << 2); /* 24Mhz */ - - if (!cpu_init_detectedx) { - post_code(0x30); - f81216h_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE, MODE_7777); - post_code(0x31); - console_init(); - } -}
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37980 )
Change subject: mb/amd/lamar: Switch away from ROMCC_BOOTBLOCK ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/37980/1/src/mainboard/amd/lamar/boo... File src/mainboard/amd/lamar/bootblock.c:
https://review.coreboot.org/c/coreboot/+/37980/1/src/mainboard/amd/lamar/boo... PS1, Line 21: #define SB_MMIO_MISC32(x) *(volatile u32 *)(AMD_SB_ACPI_MMIO_ADDR + 0xE00 + (x)) Macros with complex values should be enclosed in parentheses
Hello build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/37980
to look at the new patch set (#2).
Change subject: mb/amd/lamar: Switch away from ROMCC_BOOTBLOCK ......................................................................
mb/amd/lamar: Switch away from ROMCC_BOOTBLOCK
Warning: not tested on hardware.
Signed-off-by: Mike Banon mikebdp2@gmail.com Change-Id: I88fbe85401c8f627d0632a627cb4724db0526576 --- M src/mainboard/amd/lamar/Kconfig M src/mainboard/amd/lamar/Kconfig.name M src/mainboard/amd/lamar/Makefile.inc A src/mainboard/amd/lamar/bootblock.c D src/mainboard/amd/lamar/romstage.c 5 files changed, 46 insertions(+), 64 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/37980/2
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37980 )
Change subject: mb/amd/lamar: Switch away from ROMCC_BOOTBLOCK ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/37980/2/src/mainboard/amd/lamar/boo... File src/mainboard/amd/lamar/bootblock.c:
https://review.coreboot.org/c/coreboot/+/37980/2/src/mainboard/amd/lamar/boo... PS2, Line 21: #define SB_MMIO_MISC32(x) *(volatile u32 *)(AMD_SB_ACPI_MMIO_ADDR + 0xE00 + (x)) Macros with complex values should be enclosed in parentheses
Mike Banon has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/37980 )
Change subject: mb/amd/lamar: Switch away from ROMCC_BOOTBLOCK ......................................................................
Abandoned
These remaining-with-ROMCC rare boards seem to be broken: even if switched away from ROMCC_BOOTBLOCK, their builds are failing because of the other reasons (unrelated to new bootblock.c file). I am abandoning their "switch away from ROMCC_BOOTBLOCK" changes (CB:37975 - CB:37982), but if anyone cares about these boards - they can restore these changes and advance. Read more at CB:37750.
-
build bot (Jenkins) (Code Review) -
Mike Banon (Code Review)