Change in coreboot[master]: soc/intel/cannonlake: Enable ISH from device

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/29274 )

Change subject: soc/intel/cannonlake: Enable ISH from device
......................................................................

soc/intel/cannonlake: Enable ISH from device

PCH ISH enabled/disabled in FSP memory init UPD, it will be match the
setting in ISH device on/off in devicetree.cb.

BUG=N/A
TEST=Build and pass on whiskey lake rvp platform.

Change-Id: I6889634bf65e7ce5cc3e3393c57c86d622f1ac68
Signed-off-by: Lijian Zhao 
Reviewed-on: https://review.coreboot.org/29274
Tested-by: build bot (Jenkins) 
Reviewed-by: Pratikkumar V Prajapati 
Reviewed-by: Bora Guvendik 
---
M src/soc/intel/cannonlake/romstage/fsp_params.c
1 file changed, 6 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Bora Guvendik: Looks good to me, approved
  Pratikkumar V Prajapati: Looks good to me, approved

diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c
index 3cfa281..8506214 100644
--- a/src/soc/intel/cannonlake/romstage/fsp_params.c
+++ b/src/soc/intel/cannonlake/romstage/fsp_params.c
@@ -25,6 +25,7 @@
 {
    unsigned int i;
    uint32_t mask = 0;
+	const struct device *dev = dev_find_slot(0, PCH_DEVFN_ISH);

/* Set IGD stolen size to 64MB. */
    m_cfg->IgdDvmt50PreAlloc = 2;
@@ -55,6 +56,11 @@
 #if IS_ENABLED(CONFIG_SOC_INTEL_COFFEELAKE)
    m_cfg->SkipMpInit = !chip_get_fsp_mp_init();
 #endif
+	/* If ISH is enabled, enable ISH elements */
+	if (!dev)
+		m_cfg->PchIshEnable = 0;
+	else
+		m_cfg->PchIshEnable = dev->enabled;
 }

void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)