HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39985 )
Change subject: mb/intel/d945gclf: Improve code formatting ......................................................................
mb/intel/d945gclf: Improve code formatting
Change-Id: I3c8d430a10562edd4404d322e78f603cae191026 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/mainboard/intel/d945gclf/devicetree.cb 1 file changed, 46 insertions(+), 46 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/39985/1
diff --git a/src/mainboard/intel/d945gclf/devicetree.cb b/src/mainboard/intel/d945gclf/devicetree.cb index 3d7e8c6..ebf63f3 100644 --- a/src/mainboard/intel/d945gclf/devicetree.cb +++ b/src/mainboard/intel/d945gclf/devicetree.cb @@ -14,22 +14,22 @@
chip northbridge/intel/i945
- device cpu_cluster 0 on - chip cpu/intel/socket_441 - device lapic 0 on end - end - end + device cpu_cluster 0 on + chip cpu/intel/socket_441 + device lapic 0 on end + end + end
register "pci_mmio_size" = "768"
- device domain 0 on - subsystemid 0x8086 0x464c inherit - device pci 00.0 on end # host bridge + device domain 0 on + subsystemid 0x8086 0x464c inherit + device pci 00.0 on end # host bridge device pci 01.0 off end # i945 PCIe root port - device pci 02.0 on end # vga controller - device pci 02.1 on end # display controller + device pci 02.0 on end # vga controller + device pci 02.1 on end # display controller
- chip southbridge/intel/i82801gx + chip southbridge/intel/i82801gx register "pirqa_routing" = "0x05" register "pirqb_routing" = "0x07" register "pirqc_routing" = "0x05" @@ -46,60 +46,60 @@ register "gpi13_routing" = "1" register "gpe0_en" = "0x20000601"
- register "ide_enable_primary" = "0x1" - register "ide_enable_secondary" = "0x0" + register "ide_enable_primary" = "0x1" + register "ide_enable_secondary" = "0x0" register "c3_latency" = "85" register "p_cnt_throttling_supported" = "0"
- register "gen1_dec" = "0x0007c0681" # SuperIO Power Management + register "gen1_dec" = "0x0007c0681" # SuperIO Power Management
- device pci 1b.0 on end # High Definition Audio - device pci 1c.0 on end # PCIe port 1 + device pci 1b.0 on end # High Definition Audio + device pci 1c.0 on end # PCIe port 1 device pci 1c.1 off end # PCIe port 2 - device pci 1c.2 on end # PCIe port 3 - device pci 1c.3 on end # PCIe port 4 - device pci 1d.0 on end # USB UHCI - device pci 1d.1 on end # USB UHCI - device pci 1d.2 on end # USB UHCI + device pci 1c.2 on end # PCIe port 3 + device pci 1c.3 on end # PCIe port 4 + device pci 1d.0 on end # USB UHCI + device pci 1d.1 on end # USB UHCI + device pci 1d.2 on end # USB UHCI device pci 1d.3 off end # USB UHCI - device pci 1d.7 on end # USB2 EHCI - device pci 1e.0 on end # PCI bridge + device pci 1d.7 on end # USB2 EHCI + device pci 1e.0 on end # PCI bridge device pci 1e.2 off end # AC'97 Audio device pci 1e.3 off end # AC'97 Modem - device pci 1f.0 on # LPC bridge - chip superio/smsc/lpc47m15x - device pnp 2e.0 off # Floppy + device pci 1f.0 on # LPC bridge + chip superio/smsc/lpc47m15x + device pnp 2e.0 off # Floppy end - device pnp 2e.3 off # Parport + device pnp 2e.3 off # Parport end - device pnp 2e.4 on - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.5 on - io 0x60 = 0x2f8 - irq 0x70 = 3 + device pnp 2e.4 on + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.5 on + io 0x60 = 0x2f8 + irq 0x70 = 3 irq 0xf1 = 4 # set IRMODE 0 # XXX not an irq - end - device pnp 2e.7 on # Keyboard+Mouse + end + device pnp 2e.7 on # Keyboard+Mouse io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 irq 0x72 = 12 - irq 0xf0 = 0x82 # HW accel A20. + irq 0xf0 = 0x82 # HW accel A20. end - device pnp 2e.8 on # GAME + device pnp 2e.8 on # GAME # all default end - device pnp 2e.a on # PME + device pnp 2e.a on # PME end - device pnp 2e.b on # MPU + device pnp 2e.b on # MPU end - end - end + end + end device pci 1f.1 off end # IDE - device pci 1f.2 on end # SATA - device pci 1f.3 on end # SMBus - end - end + device pci 1f.2 on end # SATA + device pci 1f.3 on end # SMBus + end + end end
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39985 )
Change subject: mb/intel/d945gclf: Improve code formatting ......................................................................
Patch Set 1: Code-Review+1
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39985 )
Change subject: mb/intel/d945gclf: Improve code formatting ......................................................................
Patch Set 1: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/39985/1/src/mainboard/intel/d945gcl... File src/mainboard/intel/d945gclf/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/39985/1/src/mainboard/intel/d945gcl... PS1, Line 72: end You can pick these up
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39985 )
Change subject: mb/intel/d945gclf: Improve code formatting ......................................................................
Patch Set 1:
(1 comment)
Thank you
https://review.coreboot.org/c/coreboot/+/39985/1/src/mainboard/intel/d945gcl... File src/mainboard/intel/d945gclf/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/39985/1/src/mainboard/intel/d945gcl... PS1, Line 72: end
You can pick these up
Thx Done
Hello build bot (Jenkins), Paul Menzel, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39985
to look at the new patch set (#2).
Change subject: mb/intel/d945gclf: Improve code formatting ......................................................................
mb/intel/d945gclf: Improve code formatting
Change-Id: I3c8d430a10562edd4404d322e78f603cae191026 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/mainboard/intel/d945gclf/devicetree.cb 1 file changed, 45 insertions(+), 49 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/39985/2
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39985 )
Change subject: mb/intel/d945gclf: Improve code formatting ......................................................................
Patch Set 2: Code-Review+2
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39985 )
Change subject: mb/intel/d945gclf: Improve code formatting ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39985/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/39985/2//COMMIT_MSG@7 PS2, Line 7: mb/intel/d945gclf: Improve code formatting … of devicetree
Hello build bot (Jenkins), Paul Menzel, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39985
to look at the new patch set (#3).
Change subject: mb/intel/d945gclf: Improve code formatting of devicetree ......................................................................
mb/intel/d945gclf: Improve code formatting of devicetree
Change-Id: I3c8d430a10562edd4404d322e78f603cae191026 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/mainboard/intel/d945gclf/devicetree.cb 1 file changed, 45 insertions(+), 49 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/39985/3
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39985 )
Change subject: mb/intel/d945gclf: Improve code formatting of devicetree ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39985/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/39985/2//COMMIT_MSG@7 PS2, Line 7: mb/intel/d945gclf: Improve code formatting
… of devicetree
Thx
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39985 )
Change subject: mb/intel/d945gclf: Improve code formatting of devicetree ......................................................................
Patch Set 3:
Looks like crabbybuilder segfaulted again
Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39985 )
Change subject: mb/intel/d945gclf: Improve code formatting of devicetree ......................................................................
mb/intel/d945gclf: Improve code formatting of devicetree
Change-Id: I3c8d430a10562edd4404d322e78f603cae191026 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr Reviewed-on: https://review.coreboot.org/c/coreboot/+/39985 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/intel/d945gclf/devicetree.cb 1 file changed, 45 insertions(+), 49 deletions(-)
Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved
diff --git a/src/mainboard/intel/d945gclf/devicetree.cb b/src/mainboard/intel/d945gclf/devicetree.cb index 3d7e8c6..9d81e31 100644 --- a/src/mainboard/intel/d945gclf/devicetree.cb +++ b/src/mainboard/intel/d945gclf/devicetree.cb @@ -14,22 +14,22 @@
chip northbridge/intel/i945
- device cpu_cluster 0 on - chip cpu/intel/socket_441 - device lapic 0 on end - end - end + device cpu_cluster 0 on + chip cpu/intel/socket_441 + device lapic 0 on end + end + end
register "pci_mmio_size" = "768"
- device domain 0 on - subsystemid 0x8086 0x464c inherit - device pci 00.0 on end # host bridge + device domain 0 on + subsystemid 0x8086 0x464c inherit + device pci 00.0 on end # host bridge device pci 01.0 off end # i945 PCIe root port - device pci 02.0 on end # vga controller - device pci 02.1 on end # display controller + device pci 02.0 on end # vga controller + device pci 02.1 on end # display controller
- chip southbridge/intel/i82801gx + chip southbridge/intel/i82801gx register "pirqa_routing" = "0x05" register "pirqb_routing" = "0x07" register "pirqc_routing" = "0x05" @@ -46,60 +46,56 @@ register "gpi13_routing" = "1" register "gpe0_en" = "0x20000601"
- register "ide_enable_primary" = "0x1" - register "ide_enable_secondary" = "0x0" + register "ide_enable_primary" = "0x1" + register "ide_enable_secondary" = "0x0" register "c3_latency" = "85" register "p_cnt_throttling_supported" = "0"
- register "gen1_dec" = "0x0007c0681" # SuperIO Power Management + register "gen1_dec" = "0x0007c0681" # SuperIO Power Management
- device pci 1b.0 on end # High Definition Audio - device pci 1c.0 on end # PCIe port 1 + device pci 1b.0 on end # High Definition Audio + device pci 1c.0 on end # PCIe port 1 device pci 1c.1 off end # PCIe port 2 - device pci 1c.2 on end # PCIe port 3 - device pci 1c.3 on end # PCIe port 4 - device pci 1d.0 on end # USB UHCI - device pci 1d.1 on end # USB UHCI - device pci 1d.2 on end # USB UHCI + device pci 1c.2 on end # PCIe port 3 + device pci 1c.3 on end # PCIe port 4 + device pci 1d.0 on end # USB UHCI + device pci 1d.1 on end # USB UHCI + device pci 1d.2 on end # USB UHCI device pci 1d.3 off end # USB UHCI - device pci 1d.7 on end # USB2 EHCI - device pci 1e.0 on end # PCI bridge + device pci 1d.7 on end # USB2 EHCI + device pci 1e.0 on end # PCI bridge device pci 1e.2 off end # AC'97 Audio device pci 1e.3 off end # AC'97 Modem - device pci 1f.0 on # LPC bridge - chip superio/smsc/lpc47m15x - device pnp 2e.0 off # Floppy + device pci 1f.0 on # LPC bridge + chip superio/smsc/lpc47m15x + device pnp 2e.0 off end # Floppy + device pnp 2e.3 off end # Parport + device pnp 2e.4 on + io 0x60 = 0x3f8 + irq 0x70 = 4 end - device pnp 2e.3 off # Parport - end - device pnp 2e.4 on - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.5 on - io 0x60 = 0x2f8 - irq 0x70 = 3 + device pnp 2e.5 on + io 0x60 = 0x2f8 + irq 0x70 = 3 irq 0xf1 = 4 # set IRMODE 0 # XXX not an irq - end - device pnp 2e.7 on # Keyboard+Mouse + end + device pnp 2e.7 on # Keyboard+Mouse io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 irq 0x72 = 12 - irq 0xf0 = 0x82 # HW accel A20. + irq 0xf0 = 0x82 # HW accel A20. end - device pnp 2e.8 on # GAME + device pnp 2e.8 on # GAME # all default end - device pnp 2e.a on # PME - end - device pnp 2e.b on # MPU - end - end - end + device pnp 2e.a on end # PME + device pnp 2e.b on end # MPU + end + end device pci 1f.1 off end # IDE - device pci 1f.2 on end # SATA - device pci 1f.3 on end # SMBus - end - end + device pci 1f.2 on end # SATA + device pci 1f.3 on end # SMBus + end + end end
-
Angel Pons (Code Review) -
HAOUAS Elyes (Code Review)
-
Paul Menzel (Code Review)