Ravishankar Sarawadi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37783 )
Change subject: soc/intel/tigerlake: Update chip files ......................................................................
soc/intel/tigerlake: Update chip files
Update chip files to include : - new PCH devices, remove unsuportted - update soc_intel_tigerlake_config struct
BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board
Signed-off-by: Ravi Sarawadi ravishankar.sarawadi@intel.com Change-Id: Ie1518a7ffa69079fe82232afe229d9e1ffe29067 --- M src/soc/intel/tigerlake/chip.c M src/soc/intel/tigerlake/chip.h 2 files changed, 54 insertions(+), 88 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/37783/1
diff --git a/src/soc/intel/tigerlake/chip.c b/src/soc/intel/tigerlake/chip.c index 530893c..44e1e51 100644 --- a/src/soc/intel/tigerlake/chip.c +++ b/src/soc/intel/tigerlake/chip.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corp. + * Copyright (C) 2018 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -34,6 +34,38 @@ if (dev->path.type == DEVICE_PATH_DOMAIN) return "PCI0";
+ if (dev->path.type == DEVICE_PATH_USB) { + switch (dev->path.usb.port_type) { + case 0: + /* Root Hub */ + return "RHUB"; + case 2: + /* USB2 ports */ + switch (dev->path.usb.port_id) { + case 0: return "HS01"; + case 1: return "HS02"; + case 2: return "HS03"; + case 3: return "HS04"; + case 4: return "HS05"; + case 5: return "HS06"; + case 6: return "HS07"; + case 7: return "HS08"; + case 8: return "HS09"; + case 9: return "HS10"; + } + break; + case 3: + /* USB3 ports */ + switch (dev->path.usb.port_id) { + case 0: return "SS01"; + case 1: return "SS02"; + case 2: return "SS03"; + case 3: return "SS04"; + } + break; + } + return NULL; +} if (dev->path.type != DEVICE_PATH_PCI) return NULL;
@@ -43,20 +75,20 @@ case PCH_DEVFN_ISH: return "ISHB"; case PCH_DEVFN_XHCI: return "XHCI"; case PCH_DEVFN_USBOTG: return "XDCI"; - case PCH_DEVFN_THERMAL: return "THRM"; case PCH_DEVFN_I2C0: return "I2C0"; case PCH_DEVFN_I2C1: return "I2C1"; case PCH_DEVFN_I2C2: return "I2C2"; case PCH_DEVFN_I2C3: return "I2C3"; + case PCH_DEVFN_I2C4: return "I2C4"; + case PCH_DEVFN_I2C5: return "I2C5"; + case PCH_DEVFN_I2C6: return "I2C6"; + case PCH_DEVFN_I2C7: return "I2C7"; case PCH_DEVFN_CSE: return "CSE1"; case PCH_DEVFN_CSE_2: return "CSE2"; case PCH_DEVFN_CSE_IDER: return "CSED"; case PCH_DEVFN_CSE_KT: return "CSKT"; case PCH_DEVFN_CSE_3: return "CSE3"; case PCH_DEVFN_SATA: return "SATA"; - case PCH_DEVFN_UART2: return "UAR2"; - case PCH_DEVFN_I2C4: return "I2C4"; - case PCH_DEVFN_I2C5: return "I2C5"; case PCH_DEVFN_PCIE1: return "RP01"; case PCH_DEVFN_PCIE2: return "RP02"; case PCH_DEVFN_PCIE3: return "RP03"; @@ -73,21 +105,20 @@ case PCH_DEVFN_PCIE14: return "RP14"; case PCH_DEVFN_PCIE15: return "RP15"; case PCH_DEVFN_PCIE16: return "RP16"; - case PCH_DEVFN_PCIE17: return "RP17"; - case PCH_DEVFN_PCIE18: return "RP18"; - case PCH_DEVFN_PCIE19: return "RP19"; - case PCH_DEVFN_PCIE20: return "RP20"; - case PCH_DEVFN_PCIE21: return "RP21"; - case PCH_DEVFN_PCIE22: return "RP22"; - case PCH_DEVFN_PCIE23: return "RP23"; - case PCH_DEVFN_PCIE24: return "RP24"; case PCH_DEVFN_UART0: return "UAR0"; case PCH_DEVFN_UART1: return "UAR1"; + case PCH_DEVFN_UART2: return "UAR2"; + case PCH_DEVFN_UART3: return "UAR3"; + case PCH_DEVFN_UART4: return "UAR4"; + case PCH_DEVFN_UART5: return "UAR5"; + case PCH_DEVFN_UART6: return "UAR6"; case PCH_DEVFN_GSPI0: return "SPI0"; case PCH_DEVFN_GSPI1: return "SPI1"; case PCH_DEVFN_GSPI2: return "SPI2"; - case PCH_DEVFN_EMMC: return "EMMC"; - case PCH_DEVFN_SDCARD: return "SDXC"; + case PCH_DEVFN_GSPI3: return "SPI3"; + case PCH_DEVFN_GSPI4: return "SPI4"; + case PCH_DEVFN_GSPI5: return "SPI5"; + case PCH_DEVFN_GSPI6: return "SPI6"; /* Keeping ACPI device name coherent with ec.asl */ case PCH_DEVFN_ESPI: return "LPCB"; case PCH_DEVFN_P2SB: return "P2SB"; @@ -103,22 +134,6 @@ } #endif
-/* SoC rotine to fill GPIO PM mask and value for GPIO_MISCCFG register */ -static void soc_fill_gpio_pm_configuration(void) -{ - uint8_t value[TOTAL_GPIO_COMM]; - const config_t *config = config_of_soc(); - - if (config->gpio_override_pm) - memcpy(value, config->gpio_pm, sizeof(uint8_t) * - TOTAL_GPIO_COMM); - else - memset(value, MISCCFG_ENABLE_GPIO_PM_CONFIG, sizeof(uint8_t) * - TOTAL_GPIO_COMM); - - gpio_pm_configure(value, TOTAL_GPIO_COMM); -} - void soc_init_pre_device(void *chip_info) { /* Snapshot the current GPIO IRQ polarities. FSP is setting a @@ -133,8 +148,6 @@
/* Restore GPIO IRQ polarities back to previous settings. */ itss_restore_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); - - soc_fill_gpio_pm_configuration(); }
static void pci_domain_set_resources(struct device *dev) diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index 5e0fcd1..7131203 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -96,7 +96,6 @@ SaGv_Enabled, } SaGv;
- /* Rank Margin Tool. 1:Enable, 0:Disable */ uint8_t RMT;
@@ -116,22 +115,6 @@ uint8_t SataPortsEnable[8]; uint8_t SataPortsDevSlp[8];
- /* Audio related */ - uint8_t PchHdaEnable; - uint8_t PchHdaDspEnable; - - /* Enable/Disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1 */ - uint8_t PchHdaAudioLinkHda; - uint8_t PchHdaAudioLinkDmic0; - uint8_t PchHdaAudioLinkDmic1; - uint8_t PchHdaAudioLinkSsp0; - uint8_t PchHdaAudioLinkSsp1; - uint8_t PchHdaAudioLinkSsp2; - uint8_t PchHdaAudioLinkSndw1; - uint8_t PchHdaAudioLinkSndw2; - uint8_t PchHdaAudioLinkSndw3; - uint8_t PchHdaAudioLinkSndw4; - /* PCIe Root Ports */ uint8_t PcieRpEnable[CONFIG_MAX_ROOT_PORTS]; /* PCIe output clocks type to Pcie devices. @@ -145,23 +128,6 @@ /* SMBus */ uint8_t SmbusEnable;
- /* eMMC and SD */ - uint8_t ScsEmmcHs400Enabled; - /* Need to update DLL setting to get Emmc running at HS400 speed */ - uint8_t EmmcUseCustomDlls; - uint32_t EmmcTxCmdDelayRegValue; - uint32_t EmmcTxDataDelay1RegValue; - uint32_t EmmcTxDataDelay2RegValue; - uint32_t EmmcRxCmdDataDelay1RegValue; - uint32_t EmmcRxCmdDataDelay2RegValue; - uint32_t EmmcRxStrobeDelayRegValue; - - /* Enable if SD Card Power Enable Signal is Active High */ - uint8_t SdCardPowerEnableActiveHigh; - - /* Integrated Sensor */ - uint8_t PchIshEnable; - /* Heci related */ uint8_t Heci3Enabled;
@@ -198,11 +164,17 @@ /* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */ uint8_t eist_enable;
+ /* Statically clock gate 8254 PIT. */ + uint8_t clock_gate_8254; /* Enable C6 DRAM */ uint8_t enable_c6dram; - + /* + * PRMRR size setting with below options + * 0x00100000 - 1MiB + * 0x02000000 - 32MiB and beyond + */ + uint32_t PrmrrSize; uint8_t PmTimerDisabled; - /* Desired platform debug type. */ enum { DebugConsent_Disabled, @@ -248,25 +220,6 @@ FORCE_ENABLE, FORCE_DISABLE, } CnviBtAudioOffload; - - /* - * Override GPIO PM configuration: - * 0: Use FSP default GPIO PM program, - * 1: coreboot to override GPIO PM program - */ - uint8_t gpio_override_pm; - - /* - * GPIO PM configuration: 0 to disable, 1 to enable power gating - * Bit 6-7: Reserved - * Bit 5: MISCCFG_GPSIDEDPCGEN - * Bit 4: MISCCFG_GPRCOMPCDLCGEN - * Bit 3: MISCCFG_GPRTCDLCGEN - * Bit 2: MISCCFG_GSXLCGEN - * Bit 1: MISCCFG_GPDPCGEN - * Bit 0: MISCCFG_GPDLCGEN - */ - uint8_t gpio_pm[TOTAL_GPIO_COMM]; };
typedef struct soc_intel_tigerlake_config config_t;
Hello Raj Astekar, Srinidhi N Kaushik, Patrick Rudolph, Subrata Banik, Nick Vaccaro, Wonkyu Kim, build bot (Jenkins), Shaunak Saha, Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/37783
to look at the new patch set (#3).
Change subject: soc/intel/tigerlake: Update chip files ......................................................................
soc/intel/tigerlake: Update chip files
Update chip files to include : - new PCH devices, remove unsuportted - update soc_intel_tigerlake_config struct - update available Debug Consent options
BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board
Signed-off-by: Ravi Sarawadi ravishankar.sarawadi@intel.com Change-Id: Ie1518a7ffa69079fe82232afe229d9e1ffe29067 --- M src/soc/intel/tigerlake/chip.c M src/soc/intel/tigerlake/chip.h 2 files changed, 62 insertions(+), 94 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/37783/3
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37783 )
Change subject: soc/intel/tigerlake: Update chip files ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/37783/3/src/soc/intel/tigerlake/chi... File src/soc/intel/tigerlake/chip.h:
https://review.coreboot.org/c/coreboot/+/37783/3/src/soc/intel/tigerlake/chi... PS3, Line 185: ProbeType2WireDciOob = 0x06, please, no space before tabs
Hello Raj Astekar, Srinidhi N Kaushik, Patrick Rudolph, Subrata Banik, Nick Vaccaro, Wonkyu Kim, build bot (Jenkins), Shaunak Saha, Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/37783
to look at the new patch set (#4).
Change subject: soc/intel/tigerlake: Update chip files ......................................................................
soc/intel/tigerlake: Update chip files
Update chip files to include : - new PCH devices, remove unsuportted - update soc_intel_tigerlake_config struct - update available Debug Consent options
BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board
Signed-off-by: Ravi Sarawadi ravishankar.sarawadi@intel.com Change-Id: Ie1518a7ffa69079fe82232afe229d9e1ffe29067 --- M src/soc/intel/tigerlake/chip.c M src/soc/intel/tigerlake/chip.h 2 files changed, 62 insertions(+), 94 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/37783/4
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37783 )
Change subject: soc/intel/tigerlake: Update chip files ......................................................................
Patch Set 4:
(4 comments)
https://review.coreboot.org/c/coreboot/+/37783/2/src/soc/intel/tigerlake/chi... File src/soc/intel/tigerlake/chip.c:
https://review.coreboot.org/c/coreboot/+/37783/2/src/soc/intel/tigerlake/chi... PS2, Line 84: case PCH_DEVFN_I2C6: return "I2C6"; : case PCH_DEVFN_I2C7: return "I2C7" Match with MAX device # in Kconfig
https://review.coreboot.org/c/coreboot/+/37783/2/src/soc/intel/tigerlake/chi... PS2, Line 104: case PCH_DEVFN_PCIE13: return "RP13"; : case PCH_DEVFN_PCIE14: return "RP14"; : case PCH_DEVFN_PCIE15: return "RP15"; : case PCH_DEVFN_PCIE16: return "RP16"; Match with MAX device # in Kconfig
https://review.coreboot.org/c/coreboot/+/37783/2/src/soc/intel/tigerlake/chi... PS2, Line 111: case PCH_DEVFN_UART3: return "UAR3"; : case PCH_DEVFN_UART4: return "UAR4"; : case PCH_DEVFN_UART5: return "UAR5"; : case PCH_DEVFN_UART6: return "UAR6"; Match with MAX device # in Kconfig
https://review.coreboot.org/c/coreboot/+/37783/2/src/soc/intel/tigerlake/chi... PS2, Line 119: case PCH_DEVFN_GSPI4: return "SPI4"; : case PCH_DEVFN_GSPI5: return "SPI5"; : case PCH_DEVFN_GSPI6: return "SPI6"; Match with MAX device # in Kconfig
Hello Raj Astekar, Srinidhi N Kaushik, Patrick Rudolph, Subrata Banik, Nick Vaccaro, Wonkyu Kim, build bot (Jenkins), Shaunak Saha, Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/37783
to look at the new patch set (#5).
Change subject: soc/intel/tigerlake: Update chip files ......................................................................
soc/intel/tigerlake: Update chip files
Update chip files to include : - new PCH devices, remove unsuportted - update soc_intel_tigerlake_config struct - update available Debug Consent options
BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board
Signed-off-by: Ravi Sarawadi ravishankar.sarawadi@intel.com Change-Id: Ie1518a7ffa69079fe82232afe229d9e1ffe29067 --- M src/soc/intel/tigerlake/chip.c M src/soc/intel/tigerlake/chip.h 2 files changed, 52 insertions(+), 98 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/37783/5
Ravishankar Sarawadi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37783 )
Change subject: soc/intel/tigerlake: Update chip files ......................................................................
Patch Set 4:
(4 comments)
https://review.coreboot.org/c/coreboot/+/37783/2/src/soc/intel/tigerlake/chi... File src/soc/intel/tigerlake/chip.c:
https://review.coreboot.org/c/coreboot/+/37783/2/src/soc/intel/tigerlake/chi... PS2, Line 84: case PCH_DEVFN_I2C6: return "I2C6"; : case PCH_DEVFN_I2C7: return "I2C7"
Match with MAX device # in Kconfig
Done
https://review.coreboot.org/c/coreboot/+/37783/2/src/soc/intel/tigerlake/chi... PS2, Line 104: case PCH_DEVFN_PCIE13: return "RP13"; : case PCH_DEVFN_PCIE14: return "RP14"; : case PCH_DEVFN_PCIE15: return "RP15"; : case PCH_DEVFN_PCIE16: return "RP16";
Match with MAX device # in Kconfig
Done
https://review.coreboot.org/c/coreboot/+/37783/2/src/soc/intel/tigerlake/chi... PS2, Line 111: case PCH_DEVFN_UART3: return "UAR3"; : case PCH_DEVFN_UART4: return "UAR4"; : case PCH_DEVFN_UART5: return "UAR5"; : case PCH_DEVFN_UART6: return "UAR6";
Match with MAX device # in Kconfig
Done
https://review.coreboot.org/c/coreboot/+/37783/2/src/soc/intel/tigerlake/chi... PS2, Line 119: case PCH_DEVFN_GSPI4: return "SPI4"; : case PCH_DEVFN_GSPI5: return "SPI5"; : case PCH_DEVFN_GSPI6: return "SPI6";
Match with MAX device # in Kconfig
Done
Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37783 )
Change subject: soc/intel/tigerlake: Update chip files ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/37783/5//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/37783/5//COMMIT_MSG@10 PS5, Line 10: - new PCH devices, remove unsuportted unsupported
Wonkyu Kim has uploaded a new patch set (#6) to the change originally created by Ravishankar Sarawadi. ( https://review.coreboot.org/c/coreboot/+/37783 )
Change subject: soc/intel/tigerlake: Update chip files ......................................................................
soc/intel/tigerlake: Update chip files
Update chip files to include : - new PCH devices, remove unsupported - update soc_intel_tigerlake_config struct - update available Debug Consent options
BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board
Signed-off-by: Ravi Sarawadi ravishankar.sarawadi@intel.com Change-Id: Ie1518a7ffa69079fe82232afe229d9e1ffe29067 --- M src/soc/intel/tigerlake/chip.c M src/soc/intel/tigerlake/chip.h 2 files changed, 52 insertions(+), 98 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/37783/6
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37783 )
Change subject: soc/intel/tigerlake: Update chip files ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/37783/5//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/37783/5//COMMIT_MSG@10 PS5, Line 10: - new PCH devices, remove unsuportted
unsupported
Done
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37783 )
Change subject: soc/intel/tigerlake: Update chip files ......................................................................
Patch Set 6: Code-Review+2
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37783 )
Change subject: soc/intel/tigerlake: Update chip files ......................................................................
Patch Set 6:
(23 comments)
https://review.coreboot.org/c/coreboot/+/37783/6//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/37783/6//COMMIT_MSG@11 PS6, Line 11: update soc_intel_tigerlake_config struct What is the motivation behind this update? I see some of the configs being dropped from this struct, but those configs either in the current or some updated form would be required eventually. Do you plan to add those later when required?
Also, I see some configs which are not used or might not ever get used for TGL, but are still left as is. What is the plan w.r.t. those configs?
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... File src/soc/intel/tigerlake/chip.h:
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 119: Audio related Some/all of these configs are going to be used eventually for enabling audio. Do you plan to add them back later on?
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 257: gpio_override_pm Why are these removed? These are required on TGL as well.
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 39: GPP_[A:G] Is this correct?
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 70: PlatformMemorySize Is this used?
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 71: SmramMask Is this used?
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 72: MrcFastBoot Is this used?
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 73: TsegSize Is this used?
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 74: MmioSize Is this used?
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 78: DdrFreqLimit Is this used?
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 82: FreqSaGvLow Is this used?
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 86: FreqSaGvMid Is this used?
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 92: SaGv_Disabled, : SaGv_FixedLow, : SaGv_FixedMid, : SaGv_FixedHigh, : SaGv_Enabled, Are these correct for TGL?
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 105: SsicPortEnable Is this used?
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 123: CONFIG_MAX_ROOT_PORTS Is this really correct?
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 126: CONFIG_MAX_ROOT_PORTS Is this really correct?
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 143: GpioIrqRoute Is this used?
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 145: SciIrqSelect Is this used?
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 147: uint8_t TcoIrqSelect; : uint8_t TcoIrqEnable; : Are these used?
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 157: /* Enable VR specific mailbox command : * 00b - no VR specific cmd sent : * 01b - VR mailbox cmd specifically for the MPS IMPV8 VR will be sent : * 10b - VR specific cmd sent for PS4 exit issue : * 11b - Reserved */ : uint8_t SendVrMbxCmd; Is this applicable for TGL?
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 180: ProbeTypeDisable = 0x00, Why is 0x01 missing?
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 187: ProbeTypeMax Do you want ProbeTypeMax to be ProbeTypeManual?
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 221: PLATFORM_POR, : FORCE_ENABLE, : FORCE_DISABLE Is this correct?
Ravishankar Sarawadi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37783 )
Change subject: soc/intel/tigerlake: Update chip files ......................................................................
Patch Set 6:
(5 comments)
I am working on other review comments to get fixed.
https://review.coreboot.org/c/coreboot/+/37783/6//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/37783/6//COMMIT_MSG@11 PS6, Line 11: update soc_intel_tigerlake_config struct
What is the motivation behind this update? I see some of the configs being dropped from this struct, […]
Yes, we are planning on adding configs per feature enabling instead of bulk landing.
About unused configs, we will clean up in this patch as necessary.
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... File src/soc/intel/tigerlake/chip.h:
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 257: gpio_override_pm
Why are these removed? These are required on TGL as well.
Ack
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 39: GPP_[A:G]
Is this correct?
Ack
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 180: ProbeTypeDisable = 0x00,
Why is 0x01 missing?
This is in sync with FSP settings where is 0x01 is not used.
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 187: ProbeTypeMax
Do you want ProbeTypeMax to be ProbeTypeManual?
Ack
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37783 )
Change subject: soc/intel/tigerlake: Update chip files ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... File src/soc/intel/tigerlake/chip.h:
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 180: ProbeTypeDisable = 0x00,
This is in sync with FSP settings where is 0x01 is not used.
What version of FSP headers?
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37783 )
Change subject: soc/intel/tigerlake: Update chip files ......................................................................
Patch Set 7:
(1 comment)
https://review.coreboot.org/c/coreboot/+/37783/3/src/soc/intel/tigerlake/chi... File src/soc/intel/tigerlake/chip.h:
https://review.coreboot.org/c/coreboot/+/37783/3/src/soc/intel/tigerlake/chi... PS3, Line 185: ProbeType2WireDciOob = 0x06,
please, no space before tabs
Done
Wonkyu Kim has uploaded a new patch set (#9) to the change originally created by Ravishankar Sarawadi. ( https://review.coreboot.org/c/coreboot/+/37783 )
Change subject: soc/intel/tigerlake: Update chip files ......................................................................
soc/intel/tigerlake: Update chip files
Update chip files to include : - new PCH devices, remove unsupported - update soc_intel_tigerlake_config struct - update available Debug Consent options
BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board
Signed-off-by: Ravi Sarawadi ravishankar.sarawadi@intel.com Change-Id: Ie1518a7ffa69079fe82232afe229d9e1ffe29067 --- M src/soc/intel/tigerlake/chip.c M src/soc/intel/tigerlake/chip.h 2 files changed, 47 insertions(+), 24 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/37783/9
Wonkyu Kim has uploaded a new patch set (#10) to the change originally created by Ravishankar Sarawadi. ( https://review.coreboot.org/c/coreboot/+/37783 )
Change subject: soc/intel/tigerlake: Update chip files ......................................................................
soc/intel/tigerlake: Update chip files
Update chip files to include : - new PCH devices, remove unsupported - update soc_intel_tigerlake_config struct - update available Debug Consent options
BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board
Signed-off-by: Ravi Sarawadi ravishankar.sarawadi@intel.com Change-Id: Ie1518a7ffa69079fe82232afe229d9e1ffe29067 --- M src/soc/intel/tigerlake/chip.c M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/include/soc/pci_devs.h 3 files changed, 83 insertions(+), 68 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/37783/10
Wonkyu Kim has uploaded a new patch set (#11) to the change originally created by Ravishankar Sarawadi. ( https://review.coreboot.org/c/coreboot/+/37783 )
Change subject: soc/intel/tigerlake: Update chip files ......................................................................
soc/intel/tigerlake: Update chip files
Update chip files to include : - Update pci_devs.h according to TGL change - Update chip.c based on update PCI dev - Update chip.h based on TGL
BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board
Signed-off-by: Ravi Sarawadi ravishankar.sarawadi@intel.com Change-Id: Ie1518a7ffa69079fe82232afe229d9e1ffe29067 --- M src/soc/intel/tigerlake/chip.c M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/include/soc/pci_devs.h 3 files changed, 83 insertions(+), 68 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/37783/11
Wonkyu Kim has uploaded a new patch set (#12) to the change originally created by Ravishankar Sarawadi. ( https://review.coreboot.org/c/coreboot/+/37783 )
Change subject: soc/intel/tigerlake: Update chip files ......................................................................
soc/intel/tigerlake: Update chip files
Update chip files to include : - Update pci_devs.h according to TGL change - Update chip.c based on update PCI dev - Update chip.h based on TGL
BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board
Signed-off-by: Ravi Sarawadi ravishankar.sarawadi@intel.com Change-Id: Ie1518a7ffa69079fe82232afe229d9e1ffe29067 --- M src/soc/intel/tigerlake/chip.c M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/include/soc/pci_devs.h 3 files changed, 91 insertions(+), 102 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/37783/12
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37783 )
Change subject: soc/intel/tigerlake: Update chip files ......................................................................
Patch Set 12:
(22 comments)
https://review.coreboot.org/c/coreboot/+/37783/6//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/37783/6//COMMIT_MSG@11 PS6, Line 11: update soc_intel_tigerlake_config struct
Yes, we are planning on adding configs per feature enabling instead of bulk landing. […]
We'll keep the change in structure and add require TGL change to avoid autobuild issue(JSL)
https://review.coreboot.org/c/coreboot/+/37783/11/src/soc/intel/tigerlake/ch... File src/soc/intel/tigerlake/chip.h:
https://review.coreboot.org/c/coreboot/+/37783/11/src/soc/intel/tigerlake/ch... PS11, Line 200: /* Statically clock gate 8254 PIT. */ : uint8_t clock_gate_8254; Not used: Remove
https://review.coreboot.org/c/coreboot/+/37783/11/src/soc/intel/tigerlake/ch... PS11, Line 204: /* : * PRMRR size setting with below options : * 0x00100000 - 1MiB : * 0x02000000 - 32MiB and beyond : */ Update comments
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... File src/soc/intel/tigerlake/chip.h:
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 39: GPP_[A:G]
Ack
That's correct according to latest GPIO change
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 70: PlatformMemorySize
Is this used?
Used by TGL FSP
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 71: SmramMask
Is this used?
Not used: Remove
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 72: MrcFastBoot
Is this used?
Not used: remove
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 73: TsegSize
Is this used?
Used by TGL FSP
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 74: MmioSize
Is this used?
Not used: Remove
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 78: DdrFreqLimit
Is this used?
Not used: Remove
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 82: FreqSaGvLow
Is this used?
Not used: Remove
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 86: FreqSaGvMid
Is this used?
Not used: Remove
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 92: SaGv_Disabled, : SaGv_FixedLow, : SaGv_FixedMid, : SaGv_FixedHigh, : SaGv_Enabled,
Are these correct for TGL?
Update according to TGL FSP
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 105: SsicPortEnable
Is this used?
Not used : remove
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 123: CONFIG_MAX_ROOT_PORTS
Is this really correct?
TGL FSP does not use all but use this Max value to support JSL or other platform.
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 126: CONFIG_MAX_ROOT_PORTS
Is this really correct?
TGL FSP does not use all but use this Max value to support JSL or other platform.
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 143: GpioIrqRoute
Is this used?
Not used: Remove
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 145: SciIrqSelect
Is this used?
Not used: Remove
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 147: uint8_t TcoIrqSelect; : uint8_t TcoIrqEnable; :
Are these used?
Not used: Remove
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 157: /* Enable VR specific mailbox command : * 00b - no VR specific cmd sent : * 01b - VR mailbox cmd specifically for the MPS IMPV8 VR will be sent : * 10b - VR specific cmd sent for PS4 exit issue : * 11b - Reserved */ : uint8_t SendVrMbxCmd;
Is this applicable for TGL?
Not used: Remove
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 180: ProbeTypeDisable = 0x00,
What version of FSP headers?
Match with FSP header
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 221: PLATFORM_POR, : FORCE_ENABLE, : FORCE_DISABLE
Is this correct?
Update based on FSP header
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37783 )
Change subject: soc/intel/tigerlake: Update chip files ......................................................................
Patch Set 12:
(3 comments)
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... File src/soc/intel/tigerlake/chip.h:
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 180: ProbeTypeDisable = 0x00,
Match with FSP header
Done
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 187: ProbeTypeMax
Ack
Done
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 221: PLATFORM_POR, : FORCE_ENABLE, : FORCE_DISABLE
Update based on FSP header
Done
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37783 )
Change subject: soc/intel/tigerlake: Update chip files ......................................................................
Patch Set 12:
(18 comments)
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... File src/soc/intel/tigerlake/chip.h:
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 39: GPP_[A:G]
That's correct according to latest GPIO change
Done
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 70: PlatformMemorySize
Used by TGL FSP
Done
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 71: SmramMask
Not used: Remove
Done
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 72: MrcFastBoot
Not used: remove
Done
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 73: TsegSize
Used by TGL FSP
Done
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 74: MmioSize
Not used: Remove
Done
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 78: DdrFreqLimit
Not used: Remove
Done
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 82: FreqSaGvLow
Not used: Remove
Done
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 86: FreqSaGvMid
Not used: Remove
Done
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 92: SaGv_Disabled, : SaGv_FixedLow, : SaGv_FixedMid, : SaGv_FixedHigh, : SaGv_Enabled,
Update according to TGL FSP
Done
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 105: SsicPortEnable
Not used : remove
Done
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 123: CONFIG_MAX_ROOT_PORTS
TGL FSP does not use all but use this Max value to support JSL or other platform.
Done
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 126: CONFIG_MAX_ROOT_PORTS
TGL FSP does not use all but use this Max value to support JSL or other platform.
Done
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 143: GpioIrqRoute
Not used: Remove
Done
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 145: SciIrqSelect
Not used: Remove
Done
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 147: uint8_t TcoIrqSelect; : uint8_t TcoIrqEnable; :
Not used: Remove
Done
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 157: /* Enable VR specific mailbox command : * 00b - no VR specific cmd sent : * 01b - VR mailbox cmd specifically for the MPS IMPV8 VR will be sent : * 10b - VR specific cmd sent for PS4 exit issue : * 11b - Reserved */ : uint8_t SendVrMbxCmd;
Not used: Remove
Done
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 167: /* Statically clock gate 8254 PIT. */ : uint8_t clock_gate_8254; Note used: Remove
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37783 )
Change subject: soc/intel/tigerlake: Update chip files ......................................................................
Patch Set 12:
(2 comments)
https://review.coreboot.org/c/coreboot/+/37783/11/src/soc/intel/tigerlake/ch... File src/soc/intel/tigerlake/chip.h:
https://review.coreboot.org/c/coreboot/+/37783/11/src/soc/intel/tigerlake/ch... PS11, Line 200: /* Statically clock gate 8254 PIT. */ : uint8_t clock_gate_8254;
Not used: Remove
Done
https://review.coreboot.org/c/coreboot/+/37783/11/src/soc/intel/tigerlake/ch... PS11, Line 204: /* : * PRMRR size setting with below options : * 0x00100000 - 1MiB : * 0x02000000 - 32MiB and beyond : */
Update comments
Done
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37783 )
Change subject: soc/intel/tigerlake: Update chip files ......................................................................
Patch Set 12: Code-Review+1
(2 comments)
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... File src/soc/intel/tigerlake/chip.h:
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 119: Audio related
Some/all of these configs are going to be used eventually for enabling audio. […]
We'll keep the variable so that we can avoid auto build failure in JSL. And we'll update this with JSL, TGL together with devicetree change
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 167: /* Statically clock gate 8254 PIT. */ : uint8_t clock_gate_8254;
Note used: Remove
Done
Wonkyu Kim has uploaded a new patch set (#13) to the change originally created by Ravishankar Sarawadi. ( https://review.coreboot.org/c/coreboot/+/37783 )
Change subject: soc/intel/tigerlake: Update chip files ......................................................................
soc/intel/tigerlake: Update chip files
Update chip files to include : - Update pci_devs.h according to TGL change - Update chip.c based on update PCI dev - Update chip.h based on TGL
Reference: PCH EDS#576591 vol1 rev1.2
BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board
Signed-off-by: Ravi Sarawadi ravishankar.sarawadi@intel.com Change-Id: Ie1518a7ffa69079fe82232afe229d9e1ffe29067 --- M src/soc/intel/tigerlake/chip.c M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/include/soc/pci_devs.h 3 files changed, 91 insertions(+), 102 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/37783/13
Wonkyu Kim has uploaded a new patch set (#14) to the change originally created by Ravishankar Sarawadi. ( https://review.coreboot.org/c/coreboot/+/37783 )
Change subject: soc/intel/tigerlake: Update chip files ......................................................................
soc/intel/tigerlake: Update chip files
Update chip files to include : - Update pci_devs.h according to TGL change - Update chip.c based on update PCI dev - Update chip.h based on TGL
Reference: PCH EDS#576591 vol1 rev1.2
BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board
Signed-off-by: Ravi Sarawadi ravishankar.sarawadi@intel.com Change-Id: Ie1518a7ffa69079fe82232afe229d9e1ffe29067 --- M src/soc/intel/tigerlake/chip.c M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/include/soc/pci_devs.h 3 files changed, 91 insertions(+), 102 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/37783/14
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37783 )
Change subject: soc/intel/tigerlake: Update chip files ......................................................................
Patch Set 14: Code-Review+1
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37783 )
Change subject: soc/intel/tigerlake: Update chip files ......................................................................
Patch Set 14: Code-Review-1
(2 comments)
https://review.coreboot.org/c/coreboot/+/37783/7/src/soc/intel/tigerlake/chi... File src/soc/intel/tigerlake/chip.c:
https://review.coreboot.org/c/coreboot/+/37783/7/src/soc/intel/tigerlake/chi... PS7, Line 56: break; needs one more indentantion level.
https://review.coreboot.org/c/coreboot/+/37783/7/src/soc/intel/tigerlake/chi... PS7, Line 68: } please put parentheses on the same level as the statement opening it.
Wonkyu Kim has uploaded a new patch set (#15) to the change originally created by Ravishankar Sarawadi. ( https://review.coreboot.org/c/coreboot/+/37783 )
Change subject: soc/intel/tigerlake: Update chip files ......................................................................
soc/intel/tigerlake: Update chip files
Update chip files to include : - Update pci_devs.h according to TGL change - Update chip.c based on update PCI dev - Update chip.h based on TGL
Reference: PCH EDS#576591 vol1 rev1.2
BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board
Signed-off-by: Ravi Sarawadi ravishankar.sarawadi@intel.com Change-Id: Ie1518a7ffa69079fe82232afe229d9e1ffe29067 --- M src/soc/intel/tigerlake/chip.c M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/include/soc/pci_devs.h 3 files changed, 91 insertions(+), 101 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/37783/15
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37783 )
Change subject: soc/intel/tigerlake: Update chip files ......................................................................
Patch Set 15:
(3 comments)
https://review.coreboot.org/c/coreboot/+/37783/7/src/soc/intel/tigerlake/chi... File src/soc/intel/tigerlake/chip.c:
https://review.coreboot.org/c/coreboot/+/37783/7/src/soc/intel/tigerlake/chi... PS7, Line 56: break;
needs one more indentantion level.
Ack
https://review.coreboot.org/c/coreboot/+/37783/7/src/soc/intel/tigerlake/chi... PS7, Line 68: }
please put parentheses on the same level as the statement opening it.
Ack
https://review.coreboot.org/c/coreboot/+/37783/7/src/soc/intel/tigerlake/chi... PS7, Line 82: case PCH_DEVFN_I2C4: return "I2C4"; Need I2C5
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37783 )
Change subject: soc/intel/tigerlake: Update chip files ......................................................................
Patch Set 15: Code-Review+1
Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37783 )
Change subject: soc/intel/tigerlake: Update chip files ......................................................................
Patch Set 15:
(1 comment)
https://review.coreboot.org/c/coreboot/+/37783/15/src/soc/intel/tigerlake/ch... File src/soc/intel/tigerlake/chip.h:
https://review.coreboot.org/c/coreboot/+/37783/15/src/soc/intel/tigerlake/ch... PS15, Line 176: * Dieable: 0x0 Disable
Wonkyu Kim has uploaded a new patch set (#16) to the change originally created by Ravishankar Sarawadi. ( https://review.coreboot.org/c/coreboot/+/37783 )
Change subject: soc/intel/tigerlake: Update chip files ......................................................................
soc/intel/tigerlake: Update chip files
Update chip files to include : - Update pci_devs.h according to TGL change - Update chip.c based on update PCI dev - Update chip.h based on TGL
Reference: PCH EDS#576591 vol1 rev1.2
BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board
Signed-off-by: Ravi Sarawadi ravishankar.sarawadi@intel.com Change-Id: Ie1518a7ffa69079fe82232afe229d9e1ffe29067 --- M src/soc/intel/tigerlake/chip.c M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/include/soc/pci_devs.h 3 files changed, 91 insertions(+), 101 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/37783/16
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37783 )
Change subject: soc/intel/tigerlake: Update chip files ......................................................................
Patch Set 16: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/37783/15/src/soc/intel/tigerlake/ch... File src/soc/intel/tigerlake/chip.h:
https://review.coreboot.org/c/coreboot/+/37783/15/src/soc/intel/tigerlake/ch... PS15, Line 176: * Dieable: 0x0
Disable
Ack
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37783 )
Change subject: soc/intel/tigerlake: Update chip files ......................................................................
Patch Set 16:
i believe u can split this CL into 2 parts
1. chip.c and .h update as per FSP UPD filling requirements 2. Update PCI B:D:F as per EDS.
No need to club both into one
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37783 )
Change subject: soc/intel/tigerlake: Update chip files ......................................................................
Patch Set 16:
Patch Set 16:
i believe u can split this CL into 2 parts
- chip.c and .h update as per FSP UPD filling requirements
- Update PCI B:D:F as per EDS.
No need to club both into one
Originally we tried to split but can't avoid auto build failure JSL as pci_dev.h and chip.c has dependency.
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37783 )
Change subject: soc/intel/tigerlake: Update chip files ......................................................................
Patch Set 16:
Patch Set 16:
Patch Set 16:
i believe u can split this CL into 2 parts
- chip.c and .h update as per FSP UPD filling requirements
- Update PCI B:D:F as per EDS.
No need to club both into one
Originally we tried to split but can't avoid auto build failure JSL as pci_dev.h and chip.c has dependency: PCH_DEVFN_GSPI3
Should we split chip.h and chip.c without PCH_DEVFN_GSPI3 change in chip.c and pci_dev.h and chip.c with PCH_DEVFN_GSPI3?
Wonkyu Kim has uploaded a new patch set (#17) to the change originally created by Ravishankar Sarawadi. ( https://review.coreboot.org/c/coreboot/+/37783 )
Change subject: soc/intel/tigerlake: Update chip files ......................................................................
soc/intel/tigerlake: Update chip files
Update chip files to include : - Update pci_devs.h according to TGL change - Update chip.c based on update PCI dev - Update chip.h based on TGL
Reference: PCH EDS#576591 vol1 rev1.2
BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board
Signed-off-by: Ravi Sarawadi ravishankar.sarawadi@intel.com Change-Id: Ie1518a7ffa69079fe82232afe229d9e1ffe29067 --- M src/soc/intel/tigerlake/chip.c M src/soc/intel/tigerlake/chip.h 2 files changed, 54 insertions(+), 57 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/37783/17
Wonkyu Kim has uploaded a new patch set (#18) to the change originally created by Ravishankar Sarawadi. ( https://review.coreboot.org/c/coreboot/+/37783 )
Change subject: soc/intel/tigerlake: Update chip files ......................................................................
soc/intel/tigerlake: Update chip files
Update chip files to include : - Update chip.c based on TGL FSP - Update chip.h based on TGL FSP
Reference: PCH EDS#576591 vol1 rev1.2
BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board
Signed-off-by: Ravi Sarawadi ravishankar.sarawadi@intel.com Change-Id: Ie1518a7ffa69079fe82232afe229d9e1ffe29067 --- M src/soc/intel/tigerlake/chip.c M src/soc/intel/tigerlake/chip.h 2 files changed, 54 insertions(+), 57 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/37783/18
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37783 )
Change subject: soc/intel/tigerlake: Update chip files ......................................................................
Patch Set 19: Code-Review+1
Patch Set 16:
Patch Set 16:
Patch Set 16:
i believe u can split this CL into 2 parts
- chip.c and .h update as per FSP UPD filling requirements
- Update PCI B:D:F as per EDS.
No need to club both into one
Originally we tried to split but can't avoid auto build failure JSL as pci_dev.h and chip.c has dependency: PCH_DEVFN_GSPI3
Should we split chip.h and chip.c without PCH_DEVFN_GSPI3 change in chip.c and pci_dev.h and chip.c with PCH_DEVFN_GSPI3?
Split patch according to feedback. - chip.c and chip.h - pci_dev.h and chip.c including new PCI dev(GSPI3)
Wonkyu Kim has uploaded a new patch set (#20) to the change originally created by Ravishankar Sarawadi. ( https://review.coreboot.org/c/coreboot/+/37783 )
Change subject: soc/intel/tigerlake: Update chip files ......................................................................
soc/intel/tigerlake: Update chip files
Update chip files to include : - Update chip.c based on TGL FSP - Update chip.h based on TGL FSP
Reference: PCH EDS#576591 vol1 rev1.2
BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board
Signed-off-by: Ravi Sarawadi ravishankar.sarawadi@intel.com Change-Id: Ie1518a7ffa69079fe82232afe229d9e1ffe29067 --- M src/soc/intel/tigerlake/chip.c M src/soc/intel/tigerlake/chip.h 2 files changed, 54 insertions(+), 57 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/37783/20
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37783 )
Change subject: soc/intel/tigerlake: Update chip files ......................................................................
Patch Set 20: Code-Review+2
Wonkyu Kim has uploaded a new patch set (#21) to the change originally created by Ravishankar Sarawadi. ( https://review.coreboot.org/c/coreboot/+/37783 )
Change subject: soc/intel/tigerlake: Update chip files ......................................................................
soc/intel/tigerlake: Update chip files
Update chip files to include : - Update chip.c based on TGL FSP - Update chip.h based on TGL FSP
BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board
Signed-off-by: Ravi Sarawadi ravishankar.sarawadi@intel.com Change-Id: Ie1518a7ffa69079fe82232afe229d9e1ffe29067 --- M src/soc/intel/tigerlake/chip.c M src/soc/intel/tigerlake/chip.h 2 files changed, 54 insertions(+), 57 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/37783/21
Wonkyu Kim has uploaded a new patch set (#22) to the change originally created by Ravishankar Sarawadi. ( https://review.coreboot.org/c/coreboot/+/37783 )
Change subject: soc/intel/tigerlake: Update chip files ......................................................................
soc/intel/tigerlake: Update chip files
Update chip files to include : - Update chip.c based on TGL FSP - Update chip.h based on TGL FSP
BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board
Signed-off-by: Ravi Sarawadi ravishankar.sarawadi@intel.com Change-Id: Ie1518a7ffa69079fe82232afe229d9e1ffe29067 --- M src/soc/intel/tigerlake/chip.c M src/soc/intel/tigerlake/chip.h 2 files changed, 54 insertions(+), 57 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/37783/22
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37783 )
Change subject: soc/intel/tigerlake: Update chip files ......................................................................
Patch Set 22:
(9 comments)
https://review.coreboot.org/c/coreboot/+/37783/22/src/soc/intel/tigerlake/ch... File src/soc/intel/tigerlake/chip.h:
https://review.coreboot.org/c/coreboot/+/37783/22/src/soc/intel/tigerlake/ch... PS22, Line 39: GPP_[A:G] or GPD This is not correct. These values need to be of the form PMC_GPP_* because they are directly configured in PMC GPIO_CFG register. Also, [A:G] is not correct. Please see latest revision here: https://review.coreboot.org/c/coreboot/+/37427/16/src/soc/intel/tigerlake/in...
https://review.coreboot.org/c/coreboot/+/37783/22/src/soc/intel/tigerlake/ch... PS22, Line 40: gpe0_dw0 Can we please name these pmc_gpe0_dw0 and so on. GPE0_DW0 values for groups in PMC GPIO_CFG and GPIO MISCCFG are very different and so it is important to name this properly.
https://review.coreboot.org/c/coreboot/+/37783/22/src/soc/intel/tigerlake/ch... PS22, Line 135: /* Need to update DLL setting to get Emmc running at HS400 speed */ : uint8_t EmmcUseCustomDlls; : uint32_t EmmcTxCmdDelayRegValue; : uint32_t EmmcTxDataDelay1RegValue; : uint32_t EmmcTxDataDelay2RegValue; : uint32_t EmmcRxCmdDataDelay1RegValue; : uint32_t EmmcRxCmdDataDelay2RegValue; : uint32_t EmmcRxStrobeDelayRegValue; soc_intel_common_config on line 36 already includes mmc_dll_params which has the same params as these. I don't think this needs to be added again.
https://review.coreboot.org/c/coreboot/+/37783/22/src/soc/intel/tigerlake/ch... PS22, Line 145: SdCardPowerEnableActiveHigh Can we please add this when/if really required? Currently, all these params are being added which are not even used in code.
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... File src/soc/intel/tigerlake/chip.h:
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 70: PlatformMemorySize
Done
But, I don't see any code actually utilizing this.
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 73: TsegSize
Done
FSP UPD is set to CONFIG_SMM_TSEG_SIZE. So, this should not be required.
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 123: CONFIG_MAX_ROOT_PORTS
Done
As far as I can see, this is the same for TGL and JSL. So, using CONFIG_MAX_ROOT_PORTS is not correct here.
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 126: CONFIG_MAX_ROOT_PORTS
Done
Same here.
https://review.coreboot.org/c/coreboot/+/37783/22/src/soc/intel/tigerlake/ch... File src/soc/intel/tigerlake/chip.c:
https://review.coreboot.org/c/coreboot/+/37783/22/src/soc/intel/tigerlake/ch... PS22, Line 124: soc_fill_gpio_pm_configuration Can you please move this change to a CL of its own. On CNL/WHL/CML, it was identified that the GPIO PM configuration needs to be done in two places. Let's add this and the gpio_override_pm and gpio_pm in chip.h in a separate CL.
Maulik V Vaghela has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37783 )
Change subject: soc/intel/tigerlake: Update chip files ......................................................................
Patch Set 22:
(1 comment)
https://review.coreboot.org/c/coreboot/+/37783/22/src/soc/intel/tigerlake/ch... File src/soc/intel/tigerlake/chip.h:
https://review.coreboot.org/c/coreboot/+/37783/22/src/soc/intel/tigerlake/ch... PS22, Line 145: SdCardPowerEnableActiveHigh
Can we please add this when/if really required? Currently, all these params are being added which ar […]
Hi Furquan, This will be needed for JSL. This parameter is to specify the polarity of Sd card power enable gpio to FSP. Since TGL and JSL are planning to use same chip.h file, It would be better to keep it.
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37783 )
Change subject: soc/intel/tigerlake: Update chip files ......................................................................
Patch Set 22:
(5 comments)
https://review.coreboot.org/c/coreboot/+/37783/22/src/soc/intel/tigerlake/ch... File src/soc/intel/tigerlake/chip.h:
https://review.coreboot.org/c/coreboot/+/37783/22/src/soc/intel/tigerlake/ch... PS22, Line 39: GPP_[A:G] or GPD
This is not correct. […]
Ack
https://review.coreboot.org/c/coreboot/+/37783/22/src/soc/intel/tigerlake/ch... PS22, Line 40: gpe0_dw0
Can we please name these pmc_gpe0_dw0 and so on. […]
Ack
https://review.coreboot.org/c/coreboot/+/37783/22/src/soc/intel/tigerlake/ch... PS22, Line 135: /* Need to update DLL setting to get Emmc running at HS400 speed */ : uint8_t EmmcUseCustomDlls; : uint32_t EmmcTxCmdDelayRegValue; : uint32_t EmmcTxDataDelay1RegValue; : uint32_t EmmcTxDataDelay2RegValue; : uint32_t EmmcRxCmdDataDelay1RegValue; : uint32_t EmmcRxCmdDataDelay2RegValue; : uint32_t EmmcRxStrobeDelayRegValue;
soc_intel_common_config on line 36 already includes mmc_dll_params which has the same params as thes […]
This is not added but it just keep the chip.h for existing Japerlake build due to mainboard which is same as ICL. Will check it again with JSL team if JSL patch can add back for eMMC if it's needed. Need to have clean up patch for JSL mainboard(devicetree.cb)
https://review.coreboot.org/c/coreboot/+/37783/22/src/soc/intel/tigerlake/ch... PS22, Line 145: SdCardPowerEnableActiveHigh
Can we please add this when/if really required? Currently, all these params are being added which ar […]
This is not added but it just keep the chip.h for existing Japerlake build due to mainboard which is same as ICL. Will check it again with JSL team if JSL patch can add back if it's needed. Need to have clean up patch for JSL mainboard(devicetree.cb)
https://review.coreboot.org/c/coreboot/+/37783/22/src/soc/intel/tigerlake/ch... File src/soc/intel/tigerlake/chip.c:
https://review.coreboot.org/c/coreboot/+/37783/22/src/soc/intel/tigerlake/ch... PS22, Line 124: soc_fill_gpio_pm_configuration
Can you please move this change to a CL of its own. […]
Ack
Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37783 )
Change subject: soc/intel/tigerlake: Update chip files ......................................................................
Patch Set 22:
(1 comment)
https://review.coreboot.org/c/coreboot/+/37783/22/src/soc/intel/tigerlake/ch... File src/soc/intel/tigerlake/chip.h:
https://review.coreboot.org/c/coreboot/+/37783/22/src/soc/intel/tigerlake/ch... PS22, Line 135: /* Need to update DLL setting to get Emmc running at HS400 speed */ : uint8_t EmmcUseCustomDlls; : uint32_t EmmcTxCmdDelayRegValue; : uint32_t EmmcTxDataDelay1RegValue; : uint32_t EmmcTxDataDelay2RegValue; : uint32_t EmmcRxCmdDataDelay1RegValue; : uint32_t EmmcRxCmdDataDelay2RegValue; : uint32_t EmmcRxStrobeDelayRegValue;
This is not added but it just keep the chip. […]
Yes, we can use the DLL params from soc_intel_common. We will need just need EmmcUseCustomDlls config for jsl here.
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37783 )
Change subject: soc/intel/tigerlake: Update chip files ......................................................................
Patch Set 22:
(6 comments)
https://review.coreboot.org/c/coreboot/+/37783/22/src/soc/intel/tigerlake/ch... File src/soc/intel/tigerlake/chip.h:
https://review.coreboot.org/c/coreboot/+/37783/22/src/soc/intel/tigerlake/ch... PS22, Line 135: /* Need to update DLL setting to get Emmc running at HS400 speed */ : uint8_t EmmcUseCustomDlls; : uint32_t EmmcTxCmdDelayRegValue; : uint32_t EmmcTxDataDelay1RegValue; : uint32_t EmmcTxDataDelay2RegValue; : uint32_t EmmcRxCmdDataDelay1RegValue; : uint32_t EmmcRxCmdDataDelay2RegValue; : uint32_t EmmcRxStrobeDelayRegValue;
Yes, we can use the DLL params from soc_intel_common. […]
Ack
https://review.coreboot.org/c/coreboot/+/37783/22/src/soc/intel/tigerlake/ch... PS22, Line 145: SdCardPowerEnableActiveHigh
This is not added but it just keep the chip. […]
Ack
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... File src/soc/intel/tigerlake/chip.h:
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 70: PlatformMemorySize
But, I don't see any code actually utilizing this.
We provide though UPD but will use FSP default value: Delete
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 73: TsegSize
FSP UPD is set to CONFIG_SMM_TSEG_SIZE. So, this should not be required.
Ack
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 123: CONFIG_MAX_ROOT_PORTS
As far as I can see, this is the same for TGL and JSL. […]
Use CONFIG_MAX_PCIE_CLOCKS
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 126: CONFIG_MAX_ROOT_PORTS
Same here.
Use CONFIG_MAX_PCIE_CLOCKS
Wonkyu Kim has uploaded a new patch set (#23) to the change originally created by Ravishankar Sarawadi. ( https://review.coreboot.org/c/coreboot/+/37783 )
Change subject: soc/intel/tigerlake: Update chip files ......................................................................
soc/intel/tigerlake: Update chip files
Update chip files to include : - Update chip.c based on TGL FSP - Update chip.h based on TGL FSP
BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board
Signed-off-by: Ravi Sarawadi ravishankar.sarawadi@intel.com Change-Id: Ie1518a7ffa69079fe82232afe229d9e1ffe29067 --- M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/chip.c M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/pmutil.c 5 files changed, 71 insertions(+), 114 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/37783/23
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37783 )
Change subject: soc/intel/tigerlake: Update chip files ......................................................................
Patch Set 23: Code-Review+1
Wonkyu Kim has uploaded a new patch set (#24) to the change originally created by Ravishankar Sarawadi. ( https://review.coreboot.org/c/coreboot/+/37783 )
Change subject: soc/intel/tigerlake: Update chip files ......................................................................
soc/intel/tigerlake: Update chip files
Update chip files to include : - Update chip.c based on TGL FSP - Update chip.h based on TGL FSP - Update Kconfig : Define CONFIG_MAX_PCIE_CLOCKS for chip.h update - Update pmc_utils.c and JSL devicetree for build failure
BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board
Signed-off-by: Ravi Sarawadi ravishankar.sarawadi@intel.com Change-Id: Ie1518a7ffa69079fe82232afe229d9e1ffe29067 --- M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/chip.c M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/pmutil.c 5 files changed, 71 insertions(+), 114 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/37783/24
Wonkyu Kim has uploaded a new patch set (#25) to the change originally created by Ravishankar Sarawadi. ( https://review.coreboot.org/c/coreboot/+/37783 )
Change subject: soc/intel/tigerlake: Update chip files ......................................................................
soc/intel/tigerlake: Update chip files
Update chip files to include : - Update chip.c based on TGL FSP - Update chip.h based on TGL FSP - Update Kconfig : Define CONFIG_MAX_PCIE_CLOCKS for chip.h update - Update pmc_utils.c and JSL devicetree for build failure
Reference PCH EDS#576591 vol1 rev1.2
BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board
Signed-off-by: Ravi Sarawadi ravishankar.sarawadi@intel.com Change-Id: Ie1518a7ffa69079fe82232afe229d9e1ffe29067 --- M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/chip.c M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/pmutil.c 5 files changed, 71 insertions(+), 114 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/37783/25
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37783 )
Change subject: soc/intel/tigerlake: Update chip files ......................................................................
Patch Set 25:
possible to split mainboard and soc code separate in this CL ?
Wonkyu Kim has uploaded a new patch set (#26) to the change originally created by Ravishankar Sarawadi. ( https://review.coreboot.org/c/coreboot/+/37783 )
Change subject: soc/intel/tigerlake: Update chip files ......................................................................
soc/intel/tigerlake: Update chip files
Update chip files to include : - Update chip.c based on TGL FSP - Update chip.h based on TGL FSP - Update Kconfig : Define CONFIG_MAX_PCIE_CLOCKS for chip.h update - Update pmc_utils.c and JSL devicetree for build failure
Reference PCH EDS#576591 vol1 rev1.2
BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board
Signed-off-by: Ravi Sarawadi ravishankar.sarawadi@intel.com Change-Id: Ie1518a7ffa69079fe82232afe229d9e1ffe29067 --- M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/chip.c M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/pmutil.c 5 files changed, 71 insertions(+), 114 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/37783/26
Wonkyu Kim has uploaded a new patch set (#27) to the change originally created by Ravishankar Sarawadi. ( https://review.coreboot.org/c/coreboot/+/37783 )
Change subject: soc/intel/tigerlake: Update chip files ......................................................................
soc/intel/tigerlake: Update chip files
Update chip files to include : - Update chip.c based on TGL FSP - Update chip.h based on TGL FSP - Update Kconfig : Define CONFIG_MAX_PCIE_CLOCKS for chip.h update - Update pmc_utils.c and JSL devicetree for build failure
Reference PCH EDS#576591 vol1 rev1.2
BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board
Signed-off-by: Ravi Sarawadi ravishankar.sarawadi@intel.com Change-Id: Ie1518a7ffa69079fe82232afe229d9e1ffe29067 --- M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/chip.c M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/pmutil.c 5 files changed, 71 insertions(+), 114 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/37783/27
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37783 )
Change subject: soc/intel/tigerlake: Update chip files ......................................................................
Patch Set 27:
(3 comments)
https://review.coreboot.org/c/coreboot/+/37783/22/src/soc/intel/tigerlake/ch... File src/soc/intel/tigerlake/chip.h:
https://review.coreboot.org/c/coreboot/+/37783/22/src/soc/intel/tigerlake/ch... PS22, Line 135: /* Need to update DLL setting to get Emmc running at HS400 speed */ : uint8_t EmmcUseCustomDlls; : uint32_t EmmcTxCmdDelayRegValue; : uint32_t EmmcTxDataDelay1RegValue; : uint32_t EmmcTxDataDelay2RegValue; : uint32_t EmmcRxCmdDataDelay1RegValue; : uint32_t EmmcRxCmdDataDelay2RegValue; : uint32_t EmmcRxStrobeDelayRegValue;
Ack
Why is EmmcUseCustomDlls required? We can just configure the EMMC DLL params in coreboot using DLL params in soc_intel_common, right?
https://review.coreboot.org/c/coreboot/+/37783/22/src/soc/intel/tigerlake/ch... PS22, Line 145: SdCardPowerEnableActiveHigh
Ack
My point is that there is no code under src/soc/intel/tigerlake which actually uses this config. Ideally, we should add both the chip config and its corresponding code in one CL so that its use can be reviewed. It also avoids having a lot of stale entries in chip.h which is what this file had initially started with for tigerlake.
https://review.coreboot.org/c/coreboot/+/37783/22/src/soc/intel/tigerlake/ch... File src/soc/intel/tigerlake/chip.c:
https://review.coreboot.org/c/coreboot/+/37783/22/src/soc/intel/tigerlake/ch... PS22, Line 124: soc_fill_gpio_pm_configuration
Ack
Apologize for the confusion. Gerrit was initially showing this function as something new that you were adding. Hence I made the comment to remove it from this CL. I probably had my diff view messed up. Can you please leave this as is? We should not add/delete GPIO PM configuration as part of this change. It should be handled separately.
Wonkyu Kim has uploaded a new patch set (#28) to the change originally created by Ravishankar Sarawadi. ( https://review.coreboot.org/c/coreboot/+/37783 )
Change subject: soc/intel/tigerlake: Update chip files ......................................................................
soc/intel/tigerlake: Update chip files
Update chip files to include : - Update chip.c based on TGL FSP - Update chip.h based on TGL FSP - Update Kconfig : Define CONFIG_MAX_PCIE_CLOCKS for chip.h update - Update pmc_utils.c and JSL devicetree for build failure
Reference PCH EDS#576591 vol1 rev1.2
BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board
Signed-off-by: Ravi Sarawadi ravishankar.sarawadi@intel.com Change-Id: Ie1518a7ffa69079fe82232afe229d9e1ffe29067 --- M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/chip.c M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/pmutil.c 5 files changed, 71 insertions(+), 93 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/37783/28
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37783 )
Change subject: soc/intel/tigerlake: Update chip files ......................................................................
Patch Set 28:
(1 comment)
https://review.coreboot.org/c/coreboot/+/37783/22/src/soc/intel/tigerlake/ch... File src/soc/intel/tigerlake/chip.c:
https://review.coreboot.org/c/coreboot/+/37783/22/src/soc/intel/tigerlake/ch... PS22, Line 124: soc_fill_gpio_pm_configuration
Apologize for the confusion. […]
Ack
Wonkyu Kim has uploaded a new patch set (#29) to the change originally created by Ravishankar Sarawadi. ( https://review.coreboot.org/c/coreboot/+/37783 )
Change subject: soc/intel/tigerlake: Update chip files ......................................................................
soc/intel/tigerlake: Update chip files
Update chip files to include : - Update chip.c based on TGL FSP - Update chip.h based on TGL FSP - Update Kconfig : Define CONFIG_MAX_PCIE_CLOCKS for chip.h update - Update pmc_utils.c and JSL devicetree for build failure
Reference PCH EDS#576591 vol1 rev1.2
BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board
Signed-off-by: Ravi Sarawadi ravishankar.sarawadi@intel.com Change-Id: Ie1518a7ffa69079fe82232afe229d9e1ffe29067 --- M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/chip.c M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/pmutil.c 5 files changed, 73 insertions(+), 93 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/37783/29
Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37783 )
Change subject: soc/intel/tigerlake: Update chip files ......................................................................
Patch Set 29: Code-Review+2
Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37783 )
Change subject: soc/intel/tigerlake: Update chip files ......................................................................
Patch Set 29: Code-Review+1
Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37783 )
Change subject: soc/intel/tigerlake: Update chip files ......................................................................
Patch Set 29: Code-Review+2
Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37783 )
Change subject: soc/intel/tigerlake: Update chip files ......................................................................
Patch Set 30:
(2 comments)
https://review.coreboot.org/c/coreboot/+/37783/22/src/soc/intel/tigerlake/ch... File src/soc/intel/tigerlake/chip.h:
https://review.coreboot.org/c/coreboot/+/37783/22/src/soc/intel/tigerlake/ch... PS22, Line 135: /* Need to update DLL setting to get Emmc running at HS400 speed */ : uint8_t EmmcUseCustomDlls; : uint32_t EmmcTxCmdDelayRegValue; : uint32_t EmmcTxDataDelay1RegValue; : uint32_t EmmcTxDataDelay2RegValue; : uint32_t EmmcRxCmdDataDelay1RegValue; : uint32_t EmmcRxCmdDataDelay2RegValue; : uint32_t EmmcRxStrobeDelayRegValue;
Why is EmmcUseCustomDlls required? We can just configure the EMMC DLL params in coreboot using DLL p […]
EmmcUseCustomDlls is required in case we want to configure custom DLL values from FSP instead of platform defaults.
Can we done via coreboot too using INTEL_COMMON_MMC_OVERRIDE, but since FSP allows custom dll programming, we can leverage that and use the soc_intel_common dll params to initialize dll tuning UPDsfor FSP. Thoughts?
https://review.coreboot.org/c/coreboot/+/37783/22/src/soc/intel/tigerlake/ch... PS22, Line 145: SdCardPowerEnableActiveHigh
My point is that there is no code under src/soc/intel/tigerlake which actually uses this config. […]
Can we keep it for JSL? JSL would use this, it would not add into unused configs.
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37783 )
Change subject: soc/intel/tigerlake: Update chip files ......................................................................
Patch Set 30:
(2 comments)
https://review.coreboot.org/c/coreboot/+/37783/22/src/soc/intel/tigerlake/ch... File src/soc/intel/tigerlake/chip.h:
https://review.coreboot.org/c/coreboot/+/37783/22/src/soc/intel/tigerlake/ch... PS22, Line 135: /* Need to update DLL setting to get Emmc running at HS400 speed */ : uint8_t EmmcUseCustomDlls; : uint32_t EmmcTxCmdDelayRegValue; : uint32_t EmmcTxDataDelay1RegValue; : uint32_t EmmcTxDataDelay2RegValue; : uint32_t EmmcRxCmdDataDelay1RegValue; : uint32_t EmmcRxCmdDataDelay2RegValue; : uint32_t EmmcRxStrobeDelayRegValue;
EmmcUseCustomDlls is required in case we want to configure custom DLL values from FSP instead of pla […]
Just curious: Are you expecting FSP to do different things based on the values that coreboot doesn't? Basically, I am trying to understand the motivation.
In case you decide to keep this config for EmmcUseCustomDlls, would you be adding code that utilizes it in follow up CL? Can you please add appropriate comment indicating the intent of this chip config.
https://review.coreboot.org/c/coreboot/+/37783/22/src/soc/intel/tigerlake/ch... PS22, Line 145: SdCardPowerEnableActiveHigh
Can we keep it for JSL? JSL would use this, it would not add into unused configs.
Ok, sounds good.
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37783 )
Change subject: soc/intel/tigerlake: Update chip files ......................................................................
Patch Set 30:
(1 comment)
https://review.coreboot.org/c/coreboot/+/37783/30/src/soc/intel/tigerlake/ch... File src/soc/intel/tigerlake/chip.c:
https://review.coreboot.org/c/coreboot/+/37783/30/src/soc/intel/tigerlake/ch... PS30, Line 91: /* Keeping ACPI device name coherent with ec.asl */ I believe this comment was intentional.
Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37783 )
Change subject: soc/intel/tigerlake: Update chip files ......................................................................
Patch Set 30:
(1 comment)
https://review.coreboot.org/c/coreboot/+/37783/22/src/soc/intel/tigerlake/ch... File src/soc/intel/tigerlake/chip.h:
https://review.coreboot.org/c/coreboot/+/37783/22/src/soc/intel/tigerlake/ch... PS22, Line 135: /* Need to update DLL setting to get Emmc running at HS400 speed */ : uint8_t EmmcUseCustomDlls; : uint32_t EmmcTxCmdDelayRegValue; : uint32_t EmmcTxDataDelay1RegValue; : uint32_t EmmcTxDataDelay2RegValue; : uint32_t EmmcRxCmdDataDelay1RegValue; : uint32_t EmmcRxCmdDataDelay2RegValue; : uint32_t EmmcRxStrobeDelayRegValue;
Just curious: Are you expecting FSP to do different things based on the values that coreboot doesn't […]
No, FSP would be programming the same set of registers. under storage controller init, it would program the platform default anyways, setting the dll tuning from FSP can avoid, setting same registers twice(FSP + Coreboot).
I think we can remove this config for now, if JSL needs to use it for custom DLL tuning then we can add again.
Wonkyu Kim has uploaded a new patch set (#31) to the change originally created by Ravishankar Sarawadi. ( https://review.coreboot.org/c/coreboot/+/37783 )
Change subject: soc/intel/tigerlake: Update chip files ......................................................................
soc/intel/tigerlake: Update chip files
Update chip files to include : - Update chip.c based on TGL FSP - Update chip.h based on TGL FSP - Update Kconfig : Define CONFIG_MAX_PCIE_CLOCKS for chip.h update - Update pmc_utils.c and JSL devicetree for build failure
Reference PCH EDS#576591 vol1 rev1.2
BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board
Signed-off-by: Ravi Sarawadi ravishankar.sarawadi@intel.com Change-Id: Ie1518a7ffa69079fe82232afe229d9e1ffe29067 --- M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/chip.c M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/pmutil.c 5 files changed, 73 insertions(+), 94 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/37783/31
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37783 )
Change subject: soc/intel/tigerlake: Update chip files ......................................................................
Patch Set 31:
(3 comments)
https://review.coreboot.org/c/coreboot/+/37783/22/src/soc/intel/tigerlake/ch... File src/soc/intel/tigerlake/chip.h:
https://review.coreboot.org/c/coreboot/+/37783/22/src/soc/intel/tigerlake/ch... PS22, Line 135: /* Need to update DLL setting to get Emmc running at HS400 speed */ : uint8_t EmmcUseCustomDlls; : uint32_t EmmcTxCmdDelayRegValue; : uint32_t EmmcTxDataDelay1RegValue; : uint32_t EmmcTxDataDelay2RegValue; : uint32_t EmmcRxCmdDataDelay1RegValue; : uint32_t EmmcRxCmdDataDelay2RegValue; : uint32_t EmmcRxStrobeDelayRegValue;
No, FSP would be programming the same set of registers. […]
Ack
https://review.coreboot.org/c/coreboot/+/37783/22/src/soc/intel/tigerlake/ch... PS22, Line 145: SdCardPowerEnableActiveHigh
Ok, sounds good.
Ack
https://review.coreboot.org/c/coreboot/+/37783/30/src/soc/intel/tigerlake/ch... File src/soc/intel/tigerlake/chip.c:
https://review.coreboot.org/c/coreboot/+/37783/30/src/soc/intel/tigerlake/ch... PS30, Line 91: /* Keeping ACPI device name coherent with ec.asl */
I believe this comment was intentional.
Ack
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37783 )
Change subject: soc/intel/tigerlake: Update chip files ......................................................................
Patch Set 31: Code-Review+1
Wonkyu Kim has uploaded a new patch set (#33) to the change originally created by Ravishankar Sarawadi. ( https://review.coreboot.org/c/coreboot/+/37783 )
Change subject: soc/intel/tigerlake: Update chip files ......................................................................
soc/intel/tigerlake: Update chip files
Update chip files to include : - Update chip.c based on TGL FSP - Update chip.h based on TGL FSP - Update Kconfig : Define CONFIG_MAX_PCIE_CLOCKS for chip.h update - Update pmc_utils.c and JSL devicetree for build failure
Reference PCH EDS#576591 vol1 rev1.2
BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board
Signed-off-by: Ravi Sarawadi ravishankar.sarawadi@intel.com Change-Id: Ie1518a7ffa69079fe82232afe229d9e1ffe29067 --- M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/chip.c M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/pmutil.c 5 files changed, 73 insertions(+), 94 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/37783/33
Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37783 )
Change subject: soc/intel/tigerlake: Update chip files ......................................................................
Patch Set 33:
(1 comment)
https://review.coreboot.org/c/coreboot/+/37783/33//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/37783/33//COMMIT_MSG@12 PS33, Line 12: - Update Kconfig : Define CONFIG_MAX_PCIE_CLOCKS for chip.h update : - Update pmc_utils.c and JSL devicetree for build failure : : Remove Kconfig and pmc_utils.c changes from summary.
Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37783 )
Change subject: soc/intel/tigerlake: Update chip files ......................................................................
Patch Set 33: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/37783/33//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/37783/33//COMMIT_MSG@12 PS33, Line 12: - Update Kconfig : Define CONFIG_MAX_PCIE_CLOCKS for chip.h update : - Update pmc_utils.c and JSL devicetree for build failure : :
Remove Kconfig and pmc_utils.c changes from summary.
Please ignore comment, my geritt config was not comparing against base, so I wasn't seeing those two other files.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37783 )
Change subject: soc/intel/tigerlake: Update chip files ......................................................................
Patch Set 33: Code-Review+2
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37783 )
Change subject: soc/intel/tigerlake: Update chip files ......................................................................
Patch Set 33: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/37783/33/src/soc/intel/tigerlake/Kc... File src/soc/intel/tigerlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/37783/33/src/soc/intel/tigerlake/Kc... PS33, Line 120: default 7 if SOC_INTEL_TIGERLAKE : default 16 if SOC_INTEL_JASPERLAKE What is this based on? I think FSP allows maximum 16 entries for ClkReq and ClkSrc. Probably, the one for TGL is based on what is really present in the SoC? However, the one for JSL doesn't seem to be doing the same thing?
Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37783 )
Change subject: soc/intel/tigerlake: Update chip files ......................................................................
Patch Set 33:
(1 comment)
https://review.coreboot.org/c/coreboot/+/37783/33/src/soc/intel/tigerlake/Kc... File src/soc/intel/tigerlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/37783/33/src/soc/intel/tigerlake/Kc... PS33, Line 120: default 7 if SOC_INTEL_TIGERLAKE : default 16 if SOC_INTEL_JASPERLAKE
What is this based on? I think FSP allows maximum 16 entries for ClkReq and ClkSrc. […]
Yes Furquan, For JSL this needs to be updated. Updated Bug below to track this as well.
https://partnerissuetracker.corp.google.com/issues/146884608#comment2
Maulik V Vaghela has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37783 )
Change subject: soc/intel/tigerlake: Update chip files ......................................................................
Patch Set 33: Code-Review+2
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37783 )
Change subject: soc/intel/tigerlake: Update chip files ......................................................................
Patch Set 34:
(1 comment)
https://review.coreboot.org/c/coreboot/+/37783/33/src/soc/intel/tigerlake/Kc... File src/soc/intel/tigerlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/37783/33/src/soc/intel/tigerlake/Kc... PS33, Line 120: default 7 if SOC_INTEL_TIGERLAKE : default 16 if SOC_INTEL_JASPERLAKE
Yes Furquan, For JSL this needs to be updated. Updated Bug below to track this as well. […]
Ack
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/37783 )
Change subject: soc/intel/tigerlake: Update chip files ......................................................................
soc/intel/tigerlake: Update chip files
Update chip files to include : - Update chip.c based on TGL FSP - Update chip.h based on TGL FSP - Update Kconfig : Define CONFIG_MAX_PCIE_CLOCKS for chip.h update - Update pmc_utils.c and JSL devicetree for build failure
Reference PCH EDS#576591 vol1 rev1.2
BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board
Signed-off-by: Ravi Sarawadi ravishankar.sarawadi@intel.com Change-Id: Ie1518a7ffa69079fe82232afe229d9e1ffe29067 Reviewed-on: https://review.coreboot.org/c/coreboot/+/37783 Reviewed-by: Nick Vaccaro nvaccaro@google.com Reviewed-by: Subrata Banik subrata.banik@intel.com Reviewed-by: Furquan Shaikh furquan@google.com Reviewed-by: Maulik V Vaghela maulik.v.vaghela@intel.com Reviewed-by: Wonkyu Kim wonkyu.kim@intel.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/chip.c M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/pmutil.c 5 files changed, 73 insertions(+), 94 deletions(-)
Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, but someone else must approve Subrata Banik: Looks good to me, approved Nick Vaccaro: Looks good to me, approved Maulik V Vaghela: Looks good to me, approved Wonkyu Kim: Looks good to me, but someone else must approve
diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb index b4ed697..854df46 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb +++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb @@ -8,9 +8,9 @@ # Note that GPE events called out in ASL code rely on this # route. i.e. If this route changes then the affected GPE # offset bits also need to be changed. - register "gpe0_dw0" = "GPP_B" - register "gpe0_dw1" = "GPP_D" - register "gpe0_dw2" = "GPP_E" + register "pmc_gpe0_dw0" = "GPP_B" + register "pmc_gpe0_dw1" = "GPP_D" + register "pmc_gpe0_dw2" = "GPP_E"
# FSP configuration register "SaGv" = "SaGv_Enabled" diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index f1ae8a8..9340f69 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -115,6 +115,11 @@ default 16 if SOC_INTEL_JASPERLAKE default 12 if SOC_INTEL_TIGERLAKE
+config MAX_PCIE_CLOCKS + int + default 7 if SOC_INTEL_TIGERLAKE + default 16 if SOC_INTEL_JASPERLAKE + config SMM_TSEG_SIZE hex default 0x800000 diff --git a/src/soc/intel/tigerlake/chip.c b/src/soc/intel/tigerlake/chip.c index d05fbdf..2637cf8 100644 --- a/src/soc/intel/tigerlake/chip.c +++ b/src/soc/intel/tigerlake/chip.c @@ -34,29 +34,51 @@ if (dev->path.type == DEVICE_PATH_DOMAIN) return "PCI0";
+ if (dev->path.type == DEVICE_PATH_USB) { + switch (dev->path.usb.port_type) { + case 0: + /* Root Hub */ + return "RHUB"; + case 2: + /* USB2 ports */ + switch (dev->path.usb.port_id) { + case 0: return "HS01"; + case 1: return "HS02"; + case 2: return "HS03"; + case 3: return "HS04"; + case 4: return "HS05"; + case 5: return "HS06"; + case 6: return "HS07"; + case 7: return "HS08"; + case 8: return "HS09"; + case 9: return "HS10"; + } + break; + case 3: + /* USB3 ports */ + switch (dev->path.usb.port_id) { + case 0: return "SS01"; + case 1: return "SS02"; + case 2: return "SS03"; + case 3: return "SS04"; + } + break; + } + return NULL; + } if (dev->path.type != DEVICE_PATH_PCI) return NULL;
switch (dev->path.pci.devfn) { case SA_DEVFN_ROOT: return "MCHC"; - case SA_DEVFN_IGD: return "GFX0"; - case PCH_DEVFN_ISH: return "ISHB"; case PCH_DEVFN_XHCI: return "XHCI"; - case PCH_DEVFN_USBOTG: return "XDCI"; - case PCH_DEVFN_THERMAL: return "THRM"; case PCH_DEVFN_I2C0: return "I2C0"; case PCH_DEVFN_I2C1: return "I2C1"; case PCH_DEVFN_I2C2: return "I2C2"; case PCH_DEVFN_I2C3: return "I2C3"; - case PCH_DEVFN_CSE: return "CSE1"; - case PCH_DEVFN_CSE_2: return "CSE2"; - case PCH_DEVFN_CSE_IDER: return "CSED"; - case PCH_DEVFN_CSE_KT: return "CSKT"; - case PCH_DEVFN_CSE_3: return "CSE3"; - case PCH_DEVFN_SATA: return "SATA"; - case PCH_DEVFN_UART2: return "UAR2"; case PCH_DEVFN_I2C4: return "I2C4"; case PCH_DEVFN_I2C5: return "I2C5"; + case PCH_DEVFN_SATA: return "SATA"; case PCH_DEVFN_PCIE1: return "RP01"; case PCH_DEVFN_PCIE2: return "RP02"; case PCH_DEVFN_PCIE3: return "RP03"; @@ -69,34 +91,17 @@ case PCH_DEVFN_PCIE10: return "RP10"; case PCH_DEVFN_PCIE11: return "RP11"; case PCH_DEVFN_PCIE12: return "RP12"; - case PCH_DEVFN_PCIE13: return "RP13"; - case PCH_DEVFN_PCIE14: return "RP14"; - case PCH_DEVFN_PCIE15: return "RP15"; - case PCH_DEVFN_PCIE16: return "RP16"; - case PCH_DEVFN_PCIE17: return "RP17"; - case PCH_DEVFN_PCIE18: return "RP18"; - case PCH_DEVFN_PCIE19: return "RP19"; - case PCH_DEVFN_PCIE20: return "RP20"; - case PCH_DEVFN_PCIE21: return "RP21"; - case PCH_DEVFN_PCIE22: return "RP22"; - case PCH_DEVFN_PCIE23: return "RP23"; - case PCH_DEVFN_PCIE24: return "RP24"; case PCH_DEVFN_UART0: return "UAR0"; case PCH_DEVFN_UART1: return "UAR1"; + case PCH_DEVFN_UART2: return "UAR2"; case PCH_DEVFN_GSPI0: return "SPI0"; case PCH_DEVFN_GSPI1: return "SPI1"; case PCH_DEVFN_GSPI2: return "SPI2"; - case PCH_DEVFN_EMMC: return "EMMC"; - case PCH_DEVFN_SDCARD: return "SDXC"; /* Keeping ACPI device name coherent with ec.asl */ case PCH_DEVFN_ESPI: return "LPCB"; - case PCH_DEVFN_P2SB: return "P2SB"; - case PCH_DEVFN_PMC: return "PMC_"; case PCH_DEVFN_HDA: return "HDAS"; case PCH_DEVFN_SMBUS: return "SBUS"; - case PCH_DEVFN_SPI: return "FSPI"; - case PCH_DEVFN_GBE: return "IGBE"; - case PCH_DEVFN_TRACEHUB:return "THUB"; + case PCH_DEVFN_GBE: return "GLAN"; }
return NULL; @@ -146,9 +151,9 @@ .read_resources = &pci_domain_read_resources, .set_resources = &pci_domain_set_resources, .scan_bus = &pci_domain_scan_bus, - #if CONFIG(HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) .acpi_name = &soc_acpi_name, - #endif +#endif };
static struct device_operations cpu_bus_ops = { diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index 5e0fcd1..4907f49 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -36,10 +36,10 @@ struct soc_intel_common_config common_soc_config;
/* Gpio group routed to each dword of the GPE0 block. Values are - * of the form GPP_[A:G] or GPD. */ - uint8_t gpe0_dw0; /* GPE0_31_0 STS/EN */ - uint8_t gpe0_dw1; /* GPE0_63_32 STS/EN */ - uint8_t gpe0_dw2; /* GPE0_95_64 STS/EN */ + * of the form PMC_GPP_[A:U] or GPD. */ + uint8_t pmc_gpe0_dw0; /* GPE0_31_0 STS/EN */ + uint8_t pmc_gpe0_dw1; /* GPE0_63_32 STS/EN */ + uint8_t pmc_gpe0_dw2; /* GPE0_95_64 STS/EN */
/* Generic IO decode ranges */ uint32_t gen1_dec; @@ -67,43 +67,25 @@ /* TCC activation offset */ uint32_t tcc_offset;
- uint64_t PlatformMemorySize; - uint8_t SmramMask; - uint8_t MrcFastBoot; - uint32_t TsegSize; - uint16_t MmioSize; - - /* DDR Frequency Limit. Maximum Memory Frequency Selections in Mhz. - * Options : 1067, 1333, 1600, 1867, 2133, 2400, 2667, 2933, 0(Auto) */ - uint16_t DdrFreqLimit; - - /* SAGV Low Frequency Selections in Mhz. - * Options : 1067, 1333, 1600, 1867, 2133, 2400, 2667, 2933, 0(Auto) */ - uint16_t FreqSaGvLow; - - /* SAGV Mid Frequency Selections in Mhz. - * Options : 1067, 1333, 1600, 1867, 2133, 2400, 2667, 2933, 0(Auto) */ - uint16_t FreqSaGvMid; - /* System Agent dynamic frequency support. Only effects ULX/ULT CPUs. * When enabled memory will be training at two different frequencies. - * 0:Disabled, 1:FixedLow, 2:FixedMid, 3:FixedHigh, 4:Enabled */ + * 0:Disabled, 1:FixedPoint0, 2:FixedPoint1, 3:FixedPoint2, + * 4:FixedPoint3, 5:Enabled */ enum { SaGv_Disabled, - SaGv_FixedLow, - SaGv_FixedMid, - SaGv_FixedHigh, + SaGv_FixedPoint0, + SaGv_FixedPoint1, + SaGv_FixedPoint2, + SaGv_FixedPoint3, SaGv_Enabled, } SaGv;
- /* Rank Margin Tool. 1:Enable, 0:Disable */ uint8_t RMT;
/* USB related */ struct usb2_port_config usb2_ports[16]; struct usb3_port_config usb3_ports[10]; - uint8_t SsicPortEnable; /* Wake Enable Bitmap for USB2 ports */ uint16_t usb2_wake_enable_bitmap; /* Wake Enable Bitmap for USB3 ports */ @@ -137,24 +119,16 @@ /* PCIe output clocks type to Pcie devices. * 0-23: PCH rootport, 0x70: LAN, 0x80: unspecified but in use, * 0xFF: not used */ - uint8_t PcieClkSrcUsage[CONFIG_MAX_ROOT_PORTS]; + uint8_t PcieClkSrcUsage[CONFIG_MAX_PCIE_CLOCKS]; /* PCIe ClkReq-to-ClkSrc mapping, number of clkreq signal assigned to * clksrc. */ - uint8_t PcieClkSrcClkReq[CONFIG_MAX_ROOT_PORTS]; + uint8_t PcieClkSrcClkReq[CONFIG_MAX_PCIE_CLOCKS];
/* SMBus */ uint8_t SmbusEnable;
/* eMMC and SD */ uint8_t ScsEmmcHs400Enabled; - /* Need to update DLL setting to get Emmc running at HS400 speed */ - uint8_t EmmcUseCustomDlls; - uint32_t EmmcTxCmdDelayRegValue; - uint32_t EmmcTxDataDelay1RegValue; - uint32_t EmmcTxDataDelay2RegValue; - uint32_t EmmcRxCmdDataDelay1RegValue; - uint32_t EmmcRxCmdDataDelay2RegValue; - uint32_t EmmcRxStrobeDelayRegValue;
/* Enable if SD Card Power Enable Signal is Active High */ uint8_t SdCardPowerEnableActiveHigh; @@ -173,14 +147,6 @@ uint32_t GraphicsConfigPtr; uint8_t Device4Enable;
- /* GPIO IRQ Select. The valid value is 14 or 15 */ - uint8_t GpioIrqRoute; - /* SCI IRQ Select. The valid value is 9, 10, 11, 20, 21, 22, 23 */ - uint8_t SciIrqSelect; - /* TCO IRQ Select. The valid value is 9, 10, 11, 20, 21, 22, 23 */ - uint8_t TcoIrqSelect; - uint8_t TcoIrqEnable; - /* HeciEnabled decides the state of Heci1 at end of boot * Setting to 0 (default) disables Heci1 and hides the device from OS */ uint8_t HeciEnabled; @@ -188,21 +154,23 @@ uint32_t tdp_pl2_override; /* Intel Speed Shift Technology */ uint8_t speed_shift_enable; - /* Enable VR specific mailbox command - * 00b - no VR specific cmd sent - * 01b - VR mailbox cmd specifically for the MPS IMPV8 VR will be sent - * 10b - VR specific cmd sent for PS4 exit issue - * 11b - Reserved */ - uint8_t SendVrMbxCmd;
/* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */ uint8_t eist_enable;
/* Enable C6 DRAM */ uint8_t enable_c6dram; - + /* + * PRMRR size setting with below options + * Disable: 0x0 + * 32MB: 0x2000000 + * 64MB: 0x4000000 + * 128 MB: 0x8000000 + * 256 MB: 0x10000000 + * 512 MB: 0x20000000 + */ + uint32_t PrmrrSize; uint8_t PmTimerDisabled; - /* Desired platform debug type. */ enum { DebugConsent_Disabled, @@ -211,6 +179,8 @@ DebugConsent_USB3_DBC, DebugConsent_XDP, /* XDP/Mipi60 */ DebugConsent_USB2_DBC, + DebugConsent_2WIRE_DCI, + DebugConsent_Manual, } DebugConsent; /* * SerialIO device mode selection: @@ -244,9 +214,8 @@
/* CNVi BT Audio Offload: Enable/Disable BT Audio Offload. */ enum { - PLATFORM_POR, - FORCE_ENABLE, FORCE_DISABLE, + FORCE_ENABLE, } CnviBtAudioOffload;
/* diff --git a/src/soc/intel/tigerlake/pmutil.c b/src/soc/intel/tigerlake/pmutil.c index 39734bb..84a93ae 100644 --- a/src/soc/intel/tigerlake/pmutil.c +++ b/src/soc/intel/tigerlake/pmutil.c @@ -189,9 +189,9 @@ config = config_of_soc();
/* Assign to out variable */ - *dw0 = config->gpe0_dw0; - *dw1 = config->gpe0_dw1; - *dw2 = config->gpe0_dw2; + *dw0 = config->pmc_gpe0_dw0; + *dw1 = config->pmc_gpe0_dw1; + *dw2 = config->pmc_gpe0_dw2; }
static int rtc_failed(uint32_t gen_pmcon_b)
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