Attention is currently required from: Angel Pons, Fred Reitberger, Jason Glenesk, Marvin Drees, Matt DeVillier, Naresh Solanki.
Hello Angel Pons, Fred Reitberger, Jason Glenesk, Marvin Drees, Matt DeVillier, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/85640?usp=email
to look at the new patch set (#13).
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Change subject: soc/amd/common/cpu/noncar: Compute core info ......................................................................
soc/amd/common/cpu/noncar: Compute core info
In some SoC like Glinda, have 1. Different CPU cores have slightly different max boost frequency, 2. Multiple L3 cache blocks of different size identified by unique ID.
Add helper function, 1. get_max_boost_frequency() to compute max boost frequenncy. 2. ap_stash_core_info() to update core_info struct with max boost frequency & all L3 cache block uniq ID & its size.
Glinda SoC has multiple L3 caches, each identified by a unique cache UID. Each core is associated with a specific L3 cache, which can be determined based on the CPU core ID.
The default implementation (x86_get_cpu_cache_info) retrieves cache information only for the current core and assumes that the same L3 cache is shared across all cores.
To accurately determine the total L3 cache size: 1. Retrieves L3 cache information for each CPU core. 2. Identifies the unique cache ID associated with each core. 3. Aggregates cache sizes for all unique cache IDs to compute the total L3 cache size, ensuring correct summation even when L3 cache blocks have different sizes.
TEST=Build for Glinda SoC, with L3 cache = 16MB + 8MB. Ran command 'dmidecode -t 7' & verified L3 cache is 24MB.
Change-Id: I46947e8ac62c903036a81642e03201e353c3dac6 Signed-off-by: Naresh Solanki naresh.solanki@9elements.com --- M src/soc/amd/common/block/cpu/noncar/cpu.c M src/soc/amd/common/block/include/amdblocks/cpu.h 2 files changed, 37 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/85640/13