Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/27036
Change subject: src: Get rid of device_t ......................................................................
src: Get rid of device_t
Use of device_t is deprecated.
Change-Id: I6adc0429ae9ecc8f726d6167a6458d9333dc515f Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/northbridge/amd/amdmct/mct_ddr3/s3utils.c M src/soc/intel/broadwell/pmutil.c M src/southbridge/intel/bd82x6x/early_pch_common.c M src/southbridge/intel/bd82x6x/early_usb_mrc.c M src/southbridge/intel/bd82x6x/pch.c M src/southbridge/intel/common/spi.c M src/southbridge/intel/lynxpoint/pmutil.c 7 files changed, 32 insertions(+), 28 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/27036/1
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c index 4100b26..bbb1d11 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c @@ -70,9 +70,9 @@ if (is_fam15h()) { uint32_t dword; #ifdef __PRE_RAM__ - device_t dev_fn1 = PCI_DEV(0, 0x18 + node, 1); + pci_devfn_t dev_fn1 = PCI_DEV(0, 0x18 + node, 1); #else - device_t dev_fn1 = dev_find_slot(0, PCI_DEVFN(0x18 + node, 1)); + struct device *dev_fn1 = dev_find_slot(0, PCI_DEVFN(0x18 + node, 1)); #endif
/* Select DCT */ @@ -92,9 +92,9 @@ if (is_fam15h()) { uint32_t dword; #ifdef __PRE_RAM__ - device_t dev_fn1 = PCI_DEV(0, 0x18 + node, 1); + pci_devfn_t dev_fn1 = PCI_DEV(0, 0x18 + node, 1); #else - device_t dev_fn1 = dev_find_slot(0, PCI_DEVFN(0x18 + node, 1)); + struct device *dev_fn1 = dev_find_slot(0, PCI_DEVFN(0x18 + node, 1)); #endif
/* Select DCT */ @@ -129,9 +129,9 @@ if (is_fam15h()) { uint32_t dword; #ifdef __PRE_RAM__ - device_t dev_fn1 = PCI_DEV(0, 0x18 + node, 1); + pci_devfn_t dev_fn1 = PCI_DEV(0, 0x18 + node, 1); #else - device_t dev_fn1 = dev_find_slot(0, PCI_DEVFN(0x18 + node, 1)); + struct device *dev_fn1 = dev_find_slot(0, PCI_DEVFN(0x18 + node, 1)); #endif
/* Select DCT */ @@ -247,9 +247,9 @@ return (((uint64_t)msr.hi) << 32) | ((uint64_t)msr.lo); }
-static uint32_t read_config32_dct_nbpstate(device_t dev, uint8_t node, uint8_t dct, uint8_t nb_pstate, uint32_t reg) { +static uint32_t read_config32_dct_nbpstate(struct device *dev, uint8_t node, uint8_t dct, uint8_t nb_pstate, uint32_t reg) { uint32_t dword; - device_t dev_fn1 = dev_find_slot(0, PCI_DEVFN(0x18 + node, 1)); + struct device *dev_fn1 = dev_find_slot(0, PCI_DEVFN(0x18 + node, 1));
/* Select DCT */ dword = pci_read_config32(dev_fn1, 0x10c); @@ -312,9 +312,9 @@
/* Load data from DCTs into data structure */ for (node = 0; node < MAX_NODES_SUPPORTED; node++) { - device_t dev_fn1 = dev_find_slot(0, PCI_DEVFN(0x18 + node, 1)); - device_t dev_fn2 = dev_find_slot(0, PCI_DEVFN(0x18 + node, 2)); - device_t dev_fn3 = dev_find_slot(0, PCI_DEVFN(0x18 + node, 3)); + struct device *dev_fn1 = dev_find_slot(0, PCI_DEVFN(0x18 + node, 1)); + struct device *dev_fn2 = dev_find_slot(0, PCI_DEVFN(0x18 + node, 2)); + struct device *dev_fn3 = dev_find_slot(0, PCI_DEVFN(0x18 + node, 3)); /* Test for node presence */ if ((!dev_fn1) || (pci_read_config32(dev_fn1, PCI_VENDOR_ID) == 0xffffffff)) { persistent_data->node[node].node_present = 0; @@ -524,9 +524,10 @@ } } #else -static void write_config32_dct_nbpstate(device_t dev, uint8_t node, uint8_t dct, uint8_t nb_pstate, uint32_t reg, uint32_t value) { +static void write_config32_dct_nbpstate(pci_devfn_t dev, uint8_t node, uint8_t dct, uint8_t nb_pstate, uint32_t reg, uint32_t value) +{ uint32_t dword; - device_t dev_fn1 = PCI_DEV(0, 0x18 + node, 1); + pci_devfn_t dev_fn1 = PCI_DEV(0, 0x18 + node, 1);
/* Select DCT */ dword = pci_read_config32(dev_fn1, 0x10c); @@ -543,7 +544,7 @@ pci_write_config32(dev, reg, value); }
-static void write_amd_dct_index_register(device_t dev, uint32_t index_ctl_reg, uint32_t index, uint32_t value) +static void write_amd_dct_index_register(pci_devfn_t dev, uint32_t index_ctl_reg, uint32_t index, uint32_t value) { uint32_t dword;
@@ -555,11 +556,11 @@ } while (!(dword & (1 << 31))); }
-static void write_amd_dct_index_register_dct(device_t dev, uint8_t node, uint8_t dct, uint32_t index_ctl_reg, uint32_t index, uint32_t value) +static void write_amd_dct_index_register_dct(pci_devfn_t dev, uint8_t node, uint8_t dct, uint32_t index_ctl_reg, uint32_t index, uint32_t value) { if (is_fam15h()) { uint32_t dword; - device_t dev_fn1 = PCI_DEV(0, 0x18 + node, 1); + pci_devfn_t dev_fn1 = PCI_DEV(0, 0x18 + node, 1);
/* Select DCT */ dword = pci_read_config32(dev_fn1, 0x10c); diff --git a/src/soc/intel/broadwell/pmutil.c b/src/soc/intel/broadwell/pmutil.c index 25624cc..3899130 100644 --- a/src/soc/intel/broadwell/pmutil.c +++ b/src/soc/intel/broadwell/pmutil.c @@ -452,7 +452,11 @@ { u8 reg8; int rtc_failed; - device_t dev = PCH_DEV_LPC; +#if defined(__SIMPLE_DEVICE__) + pci_devfn_t dev = PCH_DEV_LPC; +#else + struct device *dev = PCH_DEV_LPC; +#endif
reg8 = pci_read_config8(dev, GEN_PMCON_3); rtc_failed = reg8 & RTC_BATTERY_DEAD; diff --git a/src/southbridge/intel/bd82x6x/early_pch_common.c b/src/southbridge/intel/bd82x6x/early_pch_common.c index 2ef47a2..f1ac4f0 100644 --- a/src/southbridge/intel/bd82x6x/early_pch_common.c +++ b/src/southbridge/intel/bd82x6x/early_pch_common.c @@ -66,9 +66,9 @@ int rtc_failure(void) { #if defined(__SIMPLE_DEVICE__) - device_t dev = PCI_DEV(0, 0x1f, 0); + pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); #else - device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); + struct device *dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); #endif return !!(pci_read_config8(dev, GEN_PMCON_3) & RTC_BATTERY_DEAD); } diff --git a/src/southbridge/intel/bd82x6x/early_usb_mrc.c b/src/southbridge/intel/bd82x6x/early_usb_mrc.c index 8fac3c7..4b9061e 100644 --- a/src/southbridge/intel/bd82x6x/early_usb_mrc.c +++ b/src/southbridge/intel/bd82x6x/early_usb_mrc.c @@ -32,8 +32,8 @@ */ void enable_usb_bar(void) { - device_t usb0 = PCH_EHCI1_DEV; - device_t usb1 = PCH_EHCI2_DEV; + pci_devfn_t usb0 = PCH_EHCI1_DEV; + pci_devfn_t usb1 = PCH_EHCI2_DEV; u32 cmd;
/* USB Controller 1 */ diff --git a/src/southbridge/intel/bd82x6x/pch.c b/src/southbridge/intel/bd82x6x/pch.c index 73c84bb..7ff13a0 100644 --- a/src/southbridge/intel/bd82x6x/pch.c +++ b/src/southbridge/intel/bd82x6x/pch.c @@ -36,7 +36,7 @@ pci_devfn_t dev; dev = PCI_DEV(0, 0x1f, 0); #else - device_t dev; + struct device *dev; dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); #endif
@@ -53,7 +53,7 @@ pci_devfn_t dev; dev = PCI_DEV(0, 0x1f, 0); #else - device_t dev; + struct device *dev; dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); #endif
diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c index bd89025..180a629 100644 --- a/src/southbridge/intel/common/spi.c +++ b/src/southbridge/intel/common/spi.c @@ -298,15 +298,14 @@ uint8_t *rcrb; /* Root Complex Register Block */ uint32_t rcba; /* Root Complex Base Address */ uint8_t bios_cntl; - device_t dev; ich9_spi_regs *ich9_spi; ich7_spi_regs *ich7_spi; uint16_t hsfs;
#ifdef __SIMPLE_DEVICE__ - dev = PCI_DEV(0, 31, 0); + pci_devfn_t dev = PCI_DEV(0, 31, 0); #else - dev = dev_find_slot(0, PCI_DEVFN(31, 0)); + struct device *dev = dev_find_slot(0, PCI_DEVFN(31, 0)); #endif
pci_read_config_dword(dev, 0xf0, &rcba); diff --git a/src/southbridge/intel/lynxpoint/pmutil.c b/src/southbridge/intel/lynxpoint/pmutil.c index 00a6e65..e96d683 100644 --- a/src/southbridge/intel/lynxpoint/pmutil.c +++ b/src/southbridge/intel/lynxpoint/pmutil.c @@ -558,9 +558,9 @@ int rtc_failure(void) { #if defined(__SIMPLE_DEVICE__) - device_t dev = PCI_DEV(0, 31, 0); + pci_devfn_t dev = PCI_DEV(0, 31, 0); #else - device_t dev = dev_find_slot(0, PCI_DEVFN(31, 0)); + struct device *dev = dev_find_slot(0, PCI_DEVFN(31, 0)); #endif return !!(pci_read_config8(dev, GEN_PMCON_3) & RTC_BATTERY_DEAD); }